view venus/src/usb/FT2232D_chip.v @ 50:3dbe73bbc0a4

Verilog src: preparations for adding the keypad
author Mychaela Falconia <falcon@freecalypso.org>
date Sat, 27 Nov 2021 04:43:53 +0000
parents 9f70dc110ad7
children
line wrap: on
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/*
 * This module encapsulates the FT2232D chip and its pinout.
 */

module FT2232D_chip (GND, AGND, VCC, AVCC, VCCIOA, VCCIOB, OUT_3V3,
		USBDP, USBDM, EECS, EESK, EEDATA, RESET, RSTOUT, TEST, PWREN,
		XTIN, XTOUT, ADBUS, ACBUS, SI_WUA, BDBUS, BCBUS, SI_WUB);

input GND, AGND, VCC, AVCC, VCCIOA, VCCIOB;
output OUT_3V3;

inout USBDP, USBDM;
output EECS, EESK;
inout EEDATA;

input RESET, TEST;
output RSTOUT, PWREN;

input XTIN;
output XTOUT;

inout [7:0] ADBUS, BDBUS;
inout [3:0] ACBUS, BCBUS;
input SI_WUA, SI_WUB;

/* instantiate the package; the mapping of signals to pins is defined here */

pkg_LQFP48 pkg (.pin_1(EESK),
		.pin_2(EEDATA),
		.pin_3(VCC),
		.pin_4(RESET),
		.pin_5(RSTOUT),
		.pin_6(OUT_3V3),
		.pin_7(USBDP),
		.pin_8(USBDM),
		.pin_9(GND),
		.pin_10(SI_WUA),
		.pin_11(ACBUS[3]),
		.pin_12(ACBUS[2]),
		.pin_13(ACBUS[1]),
		.pin_14(VCCIOA),
		.pin_15(ACBUS[0]),
		.pin_16(ADBUS[7]),
		.pin_17(ADBUS[6]),
		.pin_18(GND),
		.pin_19(ADBUS[5]),
		.pin_20(ADBUS[4]),
		.pin_21(ADBUS[3]),
		.pin_22(ADBUS[2]),
		.pin_23(ADBUS[1]),
		.pin_24(ADBUS[0]),
		.pin_25(GND),
		.pin_26(SI_WUB),
		.pin_27(BCBUS[3]),
		.pin_28(BCBUS[2]),
		.pin_29(BCBUS[1]),
		.pin_30(BCBUS[0]),
		.pin_31(VCCIOB),
		.pin_32(BDBUS[7]),
		.pin_33(BDBUS[6]),
		.pin_34(GND),
		.pin_35(BDBUS[5]),
		.pin_36(BDBUS[4]),
		.pin_37(BDBUS[3]),
		.pin_38(BDBUS[2]),
		.pin_39(BDBUS[1]),
		.pin_40(BDBUS[0]),
		.pin_41(PWREN),
		.pin_42(VCC),
		.pin_43(XTIN),
		.pin_44(XTOUT),
		.pin_45(AGND),
		.pin_46(AVCC),
		.pin_47(TEST),
		.pin_48(EECS)
	);

endmodule