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view venus/src/core/RF3166.v @ 9:3ed0f7a9c489

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Venus: first version of Verilog for the Calypso core
author Mychaela Falconia <falcon@freecalypso.org>
date Fri, 19 Nov 2021 05:58:21 +0000
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module RF3166 (HB_RF_in, Band_Select, Tx_Enable, Vbatt, GND, Vramp, LB_RF_in,
		LB_RF_out, HB_RF_out);

input LB_RF_in, HB_RF_in;
input Band_Select, Tx_Enable;
input GND, Vbatt, Vramp;
output LB_RF_out, HB_RF_out;

/* instantiate the package; the mapping of signals to pins is defined here */

pkg_RF3166 pkg (.pin_1(HB_RF_in),
		.pin_2(Band_Select),
		.pin_3(Tx_Enable),
		.pin_4(Vbatt),
		.pin_5(GND),
		.pin_6(Vramp),
		.pin_7(LB_RF_in),
		.pin_8(LB_RF_out),
		.pin_9(HB_RF_out),
		.pin_10(GND),
		.pin_11(GND),
		.pin_12(GND),
		.pin_13(GND),
		.pin_14(GND),
		.pin_15(GND),
		.pin_16(GND),
		.pin_17(GND),
		.pin_18(GND),
		.pin_19(GND),
		.pin_20(GND),
		.pin_21(GND),
		.pin_22(GND),
		.pin_23(GND),
		.pin_24(GND),
		.pin_25(GND),
		.pin_26(GND),
		.pin_27(GND),
		.pin_28(GND),
		.pin_29(GND),
		.pin_30(GND),
		.pin_31(GND)
	);

endmodule