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Venus: first version of Verilog for the Calypso core
author Mychaela Falconia <falcon@freecalypso.org>
date Fri, 19 Nov 2021 05:58:21 +0000
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module clock_rf2dbb (In, Out);

input In;
output Out;

wire mid;

resistor R251 (In, mid);

capacitor C253 (mid, Out);

endmodule