FreeCalypso > hg > freecalypso-schem2
view venus/src/primitives @ 94:4502eec1e805
D405: use Nexperia part sourced from Digi-Key direct
The previously selected part was from a Digi-Key marketplace vendor,
and they seem to not actually have that part, as the order has been
in limbo for over a month - so I put in the time and effort to look
around, and found a readily available equivalent part from Nexperia.
| author | Mychaela Falconia <falcon@freecalypso.org> |
|---|---|
| date | Tue, 11 Jan 2022 19:11:22 +0000 |
| parents | 0a26e46b2fc2 |
| children |
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/* * This file defines the primitives to be instantiated from the structural * Verilog source for the board: IC package types, basic components and * subpackages to be mapped later in the MCL binding step. */ resistor numpins 2; capacitor numpins 2; inductor numpins 2; rlc_generic numpins 2; /* "any" RLC for matching network topologies */ resistor_slot mapped_pins (side1, side2); transistor_slot mapped_pins (E, B, C); mosfet mapped_pins (G, S, D); /* TI packages */ pkg_179GHH grid "pkg_179GHH.bgadef"; pkg_100GGM grid "pkg_100GGM.bgadef"; pkg_Rita_RF numpins 49; pkg_TPA6203A1 mapped_pins (BYPASS, GND, In_neg, In_pos, SHUTDOWN, VDD, Out_pos, Out_neg); /* non-TI RF components */ pkg_RF3166 numpins 31; pkg_M034F numpins 19; /* Flash+RAM MCP (two possibilities) */ pkg_TLA064 grid "pkg_TLA064.bgadef"; pkg_TLC056 grid "pkg_TLC056.bgadef"; /* misc IC packages */ pkg_LQFP48 numpins 48; pkg_IC_5pin numpins 5; pkg_IC_8pin numpins 8; pkg_SOT23_6 numpins 6; pkg_XSON6 numpins 6; /* logic IC subpackages */ buffer_slot_basic mapped_pins (A, Y); buffer_slot_od mapped_pins (A, Y); buffer_slot_3state mapped_pins (A, nOE, Y); logic_ic_common mapped_pins (Vcc, GND); x541_common mapped_pins (Vcc, GND, nOE1, nOE2); /* crystal oscillator components */ xtal_2pin_pkg numpins 2; xtal_4pin_pkg numpins 4; varactor_diode mapped_pins (A, C); /* * The reference design we are copying calls for a couple of RF chip * attenuators. They are symmetrical in that pins 1 and 2 are equally * suitable as either the input or the output, but the package shape is * asymmetrical, thus it is a PCB layout decision which pin will be the * input and which will be the output. * * We shall use a mapped_pins primitive and two different pinout mappings * at the MCL binding stage, to be selected at layout time. */ chip_attenuator mapped_pins (In, Out, GND1, GND2); /* headers */ header_2pin numpins 2; header_3pin numpins 3; header_6pin numpins 6; header_10pin numpins 10; header_14pin numpins 14; /* other connectors */ conn_3pin numpins 3; pkg_SMA_F numpins 5; pkg_TRRS_jack numpins 6; conn_miniUSB_plus4 numpins 9; /* misc peripherals */ lcd_module_fp numpins 36; pkg_SIM_socket numpins 8; pkg_buzzer numpins 4; basic_LED mapped_pins (A, C); misc_diode mapped_pins (A, C); clamp_diode_pair mapped_pins (Signal, Pos_rail, Neg_rail); switch_2pin numpins 2; switch_4pin numpins 4; test_point numpins 1; /* * Resistor footprint with two extra "virtual pins" for sensing - see * ../doc/Charging-circuit for explanation. */ resistor_with_sense mapped_pins (side1_current, side1_sense, side2_current, side2_sense); /* * The following primitives are entirely non-physical EDA artifacts * for star routing. */ starpoint_2way numpins 2; starpoint_3way numpins 3;