module lcd_subsystem (GND, VBAT, Vio, DB, RD, WR, RS, CS, RESET,
		      BL_GPIO9, BL_GPIO11, BL_GPIO12);

input GND, VBAT, Vio;

inout [15:0] DB;
input RD, WR, RS, CS, RESET;

input BL_GPIO9, BL_GPIO11, BL_GPIO12;

wire [1:3] LEDK;

lcd_module lcd (.GND(GND),
		.VCI(Vio),
		.IOVCC(Vio),
		.DB(DB),
		.RD(RD),
		.WR(WR),
		.RS(RS),
		.CS(CS),
		.RESET(RESET),
		.IM0(GND),
		.LEDA(VBAT),
		/* LEDK broken out to allow reordering for layout */
		.LEDK[1](LEDK[1]),
		.LEDK[2](LEDK[2]),
		.LEDK[3](LEDK[3])
	);

capacitor LCD_bypass_cap (Vio, GND);

bl_current_sink bl (.GND(GND),
		    .Vio(Vio),
		    .BL_GPIO9(BL_GPIO9),
		    .BL_GPIO11(BL_GPIO11),
		    .BL_GPIO12(BL_GPIO12),
		    /* LEDK broken out to allow reordering for layout */
		    .LEDK[1](LEDK[1]),
		    .LEDK[2](LEDK[2]),
		    .LEDK[3](LEDK[3])
	);

endmodule