Our Calypso+Iota chipset allows Calypso MEMIF (memory bus interface) to run at
either 2.8V or 1.8V; the choice between these two voltages is made by way of
Iota VLMEM pin strapping.  TI's Leonardo reference design had a pair of resistor
footprints connected to VLMEM (R209 pull-up for 2.8V and R210 pull-down for
1.8V), and both of these resistor footprints have been preserved by both
Openmoko and iWOW.  Our FCDEV3B, based on Openmoko, has them too.  All 3 boards
in question (OM GTA01/02, FCDEV3B and TR-800 module) use flash+RAM MCPs that run
at 2.8V, thus R209 is populated, R210 is unpopulated, and MEMIF runs at 2.8V.

On FC Venus we have an additional complication: Calypso MEMIF goes not only to
the flash+RAM MCP, but also to our big color LCD.  On the one hand our LCD
module does support split power supplies, with Vccio supporting the full range
from 1.65 to 3.6 V, and we could design our board to support both MEMIF voltage
options and thus both our current 2.8V flash+RAM MCP and hypothetical 1.8V
options.  However, this design would imply additional complexity and cost:

* We would need to run two power supply traces to our LCD: one trace to the LCD
  module's Vcc pin (needs to be 2.5 V minimum) from our Vio rail (always 2.8V),
  and another trace to the LCD module's Vccio pin from Iota VRMEM or VRRAM
  regulator output (voltage switches with VLMEM strapping).

* Because Calypso nRESET_OUT, which we use for LCD reset, is a 2.8V output
  (V-IO domain, not MEMIF), we would need to insert a dual supply translating
  buffer between this Calypso output and the LCD module's reset input.

However, because the hypothetical possibility of swapping our current 2.8V
flash+RAM MCP for a 1.8V part is just that, hypothetical and not realistic, the
Mother's decision is to simplify our Venus board design by fixing MEMIF at 2.8V.
The simplifications resulting from this decision are as follows:

* R209 and R210 are eliminated, Iota VLMEM is tied directly to UPR.

* Only one 2.8V power supply trace will need to run to the LCD module; because
  the module's Vcc and Vccio pins are directly adjacent on the FPC tail
  interface, a single trace supplying both pins will be ideal.

* No extra buffer IC on the connection from Calypso nRESET_OUT to the LCD
  module's reset input, just a direct trace.

* 2.8V supply for the LCD will be sourced from Vio (not VRMEM or VRRAM),
  matching our previous Luna platform in which only Vio is available.

When it comes to the flash+RAM MCP, we are being deliberately non-innovative:
rather than explore potentially suitable parts on our own, we copy specific
parts that have been used successfully in historical Calypso designs.  On
FCDEV3B we copied Spansion S71PL129NC0HFW4B from Pirelli DP-L10, and the current
plan for FC Venus is to copy S71PL064JA0BFW0B (smaller footprint and no reset
complications like on FCDEV3B) from the TR-800 module.  All of our potential MCP
choices from Spansion S71PL-J and S71PL-N families require a single supply
between 2.7 and 3.1 V, hence 2.8V MEMIF.