FreeCalypso > hg > freecalypso-schem2
view venus/src/core/abb_rc_network.v @ 30:74a89c0a6466
Venus MCL: add Q401 charging circuit MOSFET
author | Mychaela Falconia <falcon@freecalypso.org> |
---|---|
date | Sun, 21 Nov 2021 08:40:13 +0000 |
parents | 3ed0f7a9c489 |
children |
line wrap: on
line source
/* * In the Leonardo schematics there is an RC network in the analog I&Q * signal path between the uplink (BUL[IQ][MP]) outputs from the ABB * and the bidirectional signals which connect directly to the RF xcvr * and to Iota's downlink (BDL[IQ][MP]) inputs. * * This structural Verilog module encapsulates the RC network in question. */ module abb_rc_network (IM_bidir, IP_bidir, QM_bidir, QP_bidir, IM_abbout, IP_abbout, QM_abbout, QP_abbout); inout IM_bidir, IP_bidir, QM_bidir, QP_bidir; input IM_abbout, IP_abbout, QM_abbout, QP_abbout; wire IM_mid, IP_mid, QM_mid, QP_mid; /* resistors on the outputs from the ABB */ resistor_slot R295A (IM_abbout, IM_mid); resistor_slot R295B (IP_abbout, IP_mid); resistor_slot R295C (QP_abbout, QP_mid); resistor_slot R295D (QM_abbout, QM_mid); /* capacitors in the middle */ capacitor C295 (QM_mid, QP_mid); capacitor C296 (IM_mid, IP_mid); /* resistors joining with the bidirectional lines */ resistor_slot R296A (IM_mid, IM_bidir); resistor_slot R296B (IP_mid, IP_bidir); resistor_slot R296C (QP_mid, QP_bidir); resistor_slot R296D (QM_mid, QM_bidir); endmodule