/*
 * This Verilog module encapsulates a MOSFET in a Si9407AEY-compatible
 * SOIC-8 footprint.
 */

module Si9407AEY (G, S, D);

input G, S;
output D;

/* instantiate the package; the mapping of signals to pins is defined here */

pkg_IC_8pin pkg (.pin_1(S),
		 .pin_2(S),
		 .pin_3(S),
		 .pin_4(G),
		 .pin_5(D),
		 .pin_6(D),
		 .pin_7(D),
		 .pin_8(D)
	);

endmodule