FreeCalypso > hg > freecalypso-schem2
view venus/doc/Charging-circuit @ 47:9f5a3567d699
progress toward LCD integration
author | Mychaela Falconia <falcon@freecalypso.org> |
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date | Sat, 27 Nov 2021 02:09:46 +0000 |
parents | 1d2b57d4f1c9 |
children | cf39d9352394 |
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The battery charging circuit on FC Venus board is the one depicted on page 56 of this TI document: ftp://ftp.freecalypso.org/pub/GSM/Calypso/APN0_120.pdf Specifically, it is the circuit depicted on the right side of Figure 7-5, the circuit with the charging power source at the top and the battery at the bottom. Going from net VCHG (output of our charging control switch S701) to net VBAT (battery +ve terminal), the charging circuit consists of Q401, D404 and R407 strung in series, with R406 adjoining between Q401 and D404. The exact location of this circuit on the board will be up to the PCB layout engineer, but we expect that all 4 of the just-named components will be placed on the same side of the board (either top or bottom), with surface traces (no vias) carrying the charging current (500 mA design intent) from each component to the next. It is important to note that whichever side of the board this circuit is placed on, it will NOT be located inside either of the two shieldcan areas. Two signal traces VCCS and VBATS will need to run from wherever the charging circuit ends up residing on the board to corresponding U202 Iota chip terminals inside the baseband core shieldcan. These traces do not carry current, instead they are differential inputs to a voltage-measuring ADC, specifically measuring the voltage drop across R407 and thus deducing the current that flows through the charging circuit at each given moment. Galvanically VBAT (board-wide battery power distribution) and VBATS (one side of the differential pair measuring the voltage across R407) are the same net, but we would like them to be seen as two separate nets by our EDA tools, to facilitate proper routing. The Mother's idea is to use intnoconn feature of pcb-rnd: http://repo.hu/cgi-bin/pool.cgi?project=pcb-rnd&cmd=show&node=intnoconn More specifically, the Mother's idea is that the subcircuit representing R407 will have 4 terminals rather than 2, with terminal numbers assigned as follows: Pin 1 = resistor side 1, surface layer Pin 2 = resistor side 1, inner layer Pin 3 = resistor side 2, surface layer Pin 4 = resistor side 2, inner layer The idea is to include in-pad microvias going one layer down inside the subcircuit, and put terminals 2 and 4 on the inner layer. Terminals 1 & 2 will form one intnoconn group, and terminals 3 & 4 will form the other intnoconn group. Surface traces carrying the charging current will connect to terminals 1 and 3, whereas sensing nets VCCS and VBATS will connect to terminals 2 and 4 on the inner layer. Our current ueda source implements this idea at the netlist level; creation of the corresponding pcb-rnd subcircuit remains TBD.