/*
 * This Verilog module is the top level for the mobile domain of FC Venus,
 * i.e., everything that isn't in the USB domain.
 */

module mobile  (GND, VCHG, Host_TxD, Host_RxD, Host_RTS, Host_CTS,
		Host_DTR, Host_DCD, Host_RI, Host_TxD2, Host_RxD2,
		RPWON, nTESTRESET);

input GND, VCHG;
input Host_TxD, Host_RTS, Host_DTR, Host_TxD2;
output Host_RxD, Host_CTS, Host_DCD, Host_RI, Host_RxD2;
input RPWON, nTESTRESET;

/* all wires for the top level of the mobile domain */

wire VBAT, VSIM, Vio;

wire PWON, ON_nOFF;

wire TDI, TCK, TMS, TDO;

wire [22:0] MCU_A;
wire [15:0] MCU_D;
wire MCU_RnW, MCU_nFWE, MCU_nFOE;
wire LCD_CS, LCD_RESET;

wire GPIO1_SPKR, GPIO3_DTR, GPIO6_headset;
wire BL_GPIO9, BL_GPIO10, BL_GPIO11, BL_GPIO12;

wire RX_IRDA, RX_MODEM, CTS_MODEM;

wire [4:0] KBC, KBR;
wire DSR_LPG, BU_PWT, LT_PWL;

wire ADIN1, ADIN2, ADIN3;

wire AUXI, AUXON, AUXOP;
wire EARN, EARP;
wire HSMICBIAS, HSO, HSMICP;
wire MICBIAS, MICIN, MICIP;

wire LED_B;	/* ueda blemish */
wire LED_C;	/* actually used */

wire ICTL, PCHG, VBATS, VCCS;

wire SIM_CLK, SIM_RST, SIM_IO, SIM_CD;
wire ANTENNA;

/* instantiate the core */

core core (.GND(GND),
	   .VBAT1(VBAT),
	   .VBAT2(VBAT),
	   .VBAT3(VBAT),
	   .VSIM(VSIM),
	   .Vio(Vio),
	   .PWON(PWON),
	   .RPWON(RPWON),
	   .nTESTRESET(nTESTRESET),
	   .ON_nOFF(ON_nOFF),
	   .TDI(TDI),
	   .TDO(TDO),
	   .TCK(TCK),
	   .TMS(TMS),
	   .MCU_A(MCU_A),
	   .MCU_D(MCU_D),
	   .MCU_RnW(MCU_RnW),
	   .MCU_nFWE(MCU_nFWE),
	   .MCU_nFOE(MCU_nFOE),
	   .EXT_nCS3(LCD_CS),
	   .EXT_nCS4(),			/* not used on FC Venus */
	   /* uWire/I2C interface unused */
	   .SCLK(),
	   .SDO(),
	   .SDI_SDA(),
	   .nSCS0_SCL(),
	   .nSCS1(),
	   /* Calypso UARTs */
	   .TX_IRDA(Host_RxD2),
	   .RX_IRDA(RX_IRDA),
	   .TXIR_IRDA(),
	   .RXIR_IRDA(GND),
	   .SD_IRDA(),
	   .TX_MODEM(Host_RxD),
	   .RX_MODEM(RX_MODEM),
	   .RTS_MODEM(Host_CTS),
	   .CTS_MODEM(CTS_MODEM),
	   .DSR_LPG(DSR_LPG),
	   /* MCSI pins are GPIOs on this board, backlight control */
	   .MCSI_TXD(BL_GPIO9),
	   .MCSI_RXD(BL_GPIO10),
	   .MCSI_CLK(BL_GPIO11),
	   .MCSI_FSYNCH(BL_GPIO12),
	   .KBC(KBC),
	   .KBR(KBR),
	   .BU_PWT(BU_PWT),
	   .LT_PWL(LT_PWL),
	   .GPIO0(),
	   .GPIO1(GPIO1_SPKR),
	   .GPIO2(Host_DCD),
	   .GPIO3(GPIO3_DTR),
	   .GPIO4(),
	   .GPIO6(GPIO6_headset),
	   .GPIO7_RESETOUT(LCD_RESET),
	   .GPIO8(Host_RI),
	   .GPIO13(),
	   .ADIN1(ADIN1),
	   .ADIN2(ADIN2),
	   .ADIN3(ADIN3),
	   .DAC(),
	   .AUXI(AUXI),
	   .AUXON(AUXON),
	   .AUXOP(AUXOP),
	   .EARN(EARN),
	   .EARP(EARP),
	   .HSMICBIAS(HSMICBIAS),
	   .HSMICP(HSMICP),
	   .HSO(HSO),
	   .MICBIAS(MICBIAS),
	   .MICIN(MICIN),
	   .MICIP(MICIP),
	   .LED_A(),
	   .LED_B(LED_B),
	   .LED_C(LED_C),
	   .ICTL(ICTL),
	   .PCHG(PCHG),
	   .VBATS(VBATS),
	   .VCCS(VCCS),
	   .VCHG(VCHG),
	   .SIM_IO(SIM_IO),
	   .SIM_CLK(SIM_CLK),
	   .SIM_RST(SIM_RST),
	   .SIM_CD(SIM_CD),
	   .ANTENNA(ANTENNA)
	);

/* battery or lab bench power input */
battery batt (.VBAT(VBAT),
	      .GND(GND),
	      .Third_pin(ADIN2)
	);

/* Calypso UART inputs */
calypso_uart_in uart (  .GND(GND),
			.VBAT(VBAT),
			.Vio(Vio),
			.Host_TxD(Host_TxD),
			.Host_RTS(Host_RTS),
			.Host_DTR(Host_DTR),
			.Host_TxD2(Host_TxD2),
			.RX_MODEM(RX_MODEM),
			.CTS_MODEM(CTS_MODEM),
			.GPIO_DTR(GPIO3_DTR),
			.RX_IRDA(RX_IRDA)
	);

/* JTAG interface */
jtag_if jtag_if (.GND(GND),
		 .Vio(Vio),
		 .nTESTRESET(nTESTRESET),
		 .TDI(TDI),
		 .TCK(TCK),
		 .TMS(TMS),
		 .TDO(TDO)
	);

/* SIM socket */
sim_socket_block sim (.GND(GND),
		      .Vio(Vio),
		      .VSIM(VSIM),
		      .SIM_CLK(SIM_CLK),
		      .SIM_RST(SIM_RST),
		      .SIM_IO(SIM_IO),
		      .SIM_CD(SIM_CD)
	);

/* antenna interface */
sma_wrap SMA (.Center(ANTENNA), .Shell(GND));

endmodule