FreeCalypso > hg > freecalypso-schem2
view venus/src/periph/audio_main.v @ 83:c27854430cb3
add 3-pin header for possible external boot control
author | Mychaela Falconia <falcon@freecalypso.org> |
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date | Wed, 08 Dec 2021 05:32:47 +0000 |
parents | 3afd172b83e1 |
children |
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/* * This Verilog module encapsulates our main audio channel. */ module audio_main (GND, EARN, EARP, MICBIAS, MICIN, MICIP); input GND; input EARN, EARP; input MICBIAS; output MICIN, MICIP; /* internal wires */ wire EARN_jack, EARP_jack, MIC_jack; /* instantiate the jack */ trrs_jack jack (.T(EARP_jack), .R(MIC_jack), .R2(EARN_jack), .S(GND), .T_sw(), /* not used */ .R_sw() /* not used */ ); /* earpiece path filter caps */ capacitor C15 (EARP, EARN); capacitor C16 (EARP, GND); capacitor C17 (EARP, GND); capacitor C18 (EARN, GND); capacitor C19 (EARN, GND); /* earpiece path filter inductors */ inductor L1 (EARP, EARP_jack); inductor L2 (EARN, EARN_jack); /* microphone input circuit */ capacitor C13 (MICBIAS, GND); resistor R9 (MICBIAS, MIC_jack); capacitor C14 (MIC_jack, GND); capacitor C12 (MICBIAS, MICIP); capacitor C21 (MIC_jack, MICIN); capacitor C32 (MICIP, MICIN); endmodule