FreeCalypso > hg > freecalypso-schem2
view venus/src/core/memory.v @ 53:d9ae0e85aea2
MCL: prebiased transistor pair parts
author | Mychaela Falconia <falcon@freecalypso.org> |
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date | Sat, 27 Nov 2021 19:16:58 +0000 |
parents | 3ed0f7a9c489 |
children | 96e02b1b2374 |
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module memory (GND, Vflash, Vsram, MCU_A, MCU_D, MCU_nRD, MCU_nWR, MCU_nBHE, MCU_nBLE, Flash_RST, CS_flash1, CS_RAM); input GND, Vflash, Vsram; input [22:1] MCU_A; inout [15:0] MCU_D; input MCU_nRD, MCU_nWR, MCU_nBHE, MCU_nBLE; input Flash_RST; input CS_flash1, CS_RAM; S71PL064J chip (.Flash_Vcc(Vflash), .RAM_Vcc(Vsram), .Vss(GND), .A(MCU_A), .DQ(MCU_D), .OE(MCU_nRD), .WE(MCU_nWR), .Flash_CE1(CS_flash1), .Flash_RST(Flash_RST), .Flash_WP_ACC(Vflash), .Flash_ready_busy(), /* no connect */ .RAM_CE_actlow(CS_RAM), .RAM_CE_acthigh(Vsram), .RAM_UB(MCU_nBHE), .RAM_LB(MCU_nBLE) ); /* bypass caps */ capacitor C318 (Vsram, GND); capacitor C322 (Vflash, GND); endmodule