/*
 * This file defines the primitives to be instantiated from the structural
 * Verilog source for the board: IC package types, basic components and
 * subpackages to be mapped later in the MCL binding step.
 */

resistor	numpins 2;
capacitor	numpins 2;
inductor	numpins 2;
rlc_generic	numpins 2;	/* "any" RLC for matching network topologies */
starpoint	numpins 2;

resistor_slot	mapped_pins (side1, side2);
transistor_slot	mapped_pins (E, B, C);
mosfet		mapped_pins (G, S, D);

/* TI packages */
pkg_179GHH	grid "pkg_179GHH.bgadef";
pkg_100GGM	grid "pkg_100GGM.bgadef";
pkg_Rita_RF	numpins 49;
pkg_TPA6203A1	mapped_pins (BYPASS, GND, In_neg, In_pos, SHUTDOWN, VDD,
				Out_pos, Out_neg);

/* non-TI RF components */
pkg_RF3166	numpins 31;
pkg_M034F	numpins 19;

/* Flash+RAM MCP (two possibilities) */
pkg_TLA064	grid "pkg_TLA064.bgadef";
pkg_TLC056	grid "pkg_TLC056.bgadef";

/* misc IC packages */
pkg_XSON6	numpins 6;

/* logic IC subpackages */
buffer_slot_basic	mapped_pins (A, Y);
buffer_slot_3state	mapped_pins (A, nOE, Y);
logic_ic_common		mapped_pins (Vcc, GND);
x541_common		mapped_pins (Vcc, GND, nOE1, nOE2);

/* crystal oscillator components */
xtal_2pin_pkg	numpins 2;
xtal_4pin_pkg	numpins 4;
varactor_diode	mapped_pins (Anode, Cathode);

/*
 * The reference design we are copying calls for a couple of RF chip
 * attenuators.  They are symmetrical in that pins 1 and 2 are equally
 * suitable as either the input or the output, but the package shape is
 * asymmetrical, thus it is a PCB layout decision which pin will be the
 * input and which will be the output.
 *
 * We shall use a mapped_pins primitive and two different pinout mappings
 * at the MCL binding stage, to be selected at layout time.
 */

chip_attenuator	mapped_pins (In, Out, GND1, GND2);

/* connectors */
header_2pin	numpins 2;
conn_3pin	numpins 3;
header_14pin	numpins 14;
pkg_SMA_F	numpins 5;
pkg_TRRS_jack	numpins 6;

/* misc peripherals */
pkg_SIM_socket		numpins 8;
basic_LED		mapped_pins (Anode, Cathode);