module S71PL064J (Flash_Vcc, RAM_Vcc, Vss,
		  A, DQ, OE, WE,
		  Flash_CE1, Flash_RST,
		  Flash_WP_ACC, Flash_ready_busy,
		  RAM_CE_actlow, RAM_CE_acthigh, RAM_UB, RAM_LB);

input Flash_Vcc, RAM_Vcc, Vss;
input [21:0] A;
inout [15:0] DQ;
input OE, WE;
input Flash_CE1, Flash_RST, Flash_WP_ACC;
output Flash_ready_busy;
input RAM_CE_actlow, RAM_CE_acthigh, RAM_UB, RAM_LB;

/* instantiate the package; the mapping of signals to balls is defined here */

pkg_TLC056 pkg (.A2(A[7]),
		.A3(RAM_LB),
		.A4(Flash_WP_ACC),
		.A5(WE),
		.A6(A[8]),
		.A7(A[11]),
		.B1(A[3]),
		.B2(A[6]),
		.B3(RAM_UB),
		.B4(Flash_RST),
		.B5(RAM_CE_acthigh),
		.B6(A[19]),
		.B7(A[12]),
		.B8(A[15]),
		.C1(A[2]),
		.C2(A[5]),
		.C3(A[18]),
		.C4(Flash_ready_busy),
		.C5(A[20]),
		.C6(A[9]),
		.C7(A[13]),
		.C8(A[21]),
		.D1(A[1]),
		.D2(A[4]),
		.D3(A[17]),
		.D6(A[10]),
		.D7(A[14]),
		.D8(),		/* no connect */
		.E1(A[0]),
		.E2(Vss),
		.E3(DQ[1]),
		.E6(DQ[6]),
		.E7(),		/* no connect */
		.E8(A[16]),
		.F1(Flash_CE1),
		.F2(OE),
		.F3(DQ[9]),
		.F4(DQ[3]),
		.F5(DQ[4]),
		.F6(DQ[13]),
		.F7(DQ[15]),
		.F8(),		/* no connect */
		.G1(RAM_CE_actlow),
		.G2(DQ[0]),
		.G3(DQ[10]),
		.G4(Flash_Vcc),
		.G5(RAM_Vcc),
		.G6(DQ[12]),
		.G7(DQ[7]),
		.G8(Vss),
		.H2(DQ[8]),
		.H3(DQ[2]),
		.H4(DQ[11]),
		.H5(),		/* no connect */
		.H6(DQ[5]),
		.H7(DQ[14])
	);

endmodule