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capture initial population of RLC67[0-5]
author Mychaela Falconia <falcon@freecalypso.org>
date Sun, 05 Dec 2021 04:41:45 +0000
parents 3ed0f7a9c489
children
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module clock_rf2dbb (In, Out);

input In;
output Out;

wire mid;

resistor R251 (In, mid);

capacitor C253 (mid, Out);

endmodule