FreeCalypso > hg > freecalypso-schem2

view venus/src/usb/usb_xtal_wrap.v @ 81:fbe54d6cd082

Find changesets by keywords (author, files, the commit message), revision number or hash, or revset expression.
capture initial population of RLC67[0-5]
author Mychaela Falconia <falcon@freecalypso.org>
date Sun, 05 Dec 2021 04:41:45 +0000
parents 8f3df7a222f5
children
line wrap: on
line source

/*
 * This Verilog module encapsulates the PCB footprint
 * for our 6.0 MHz USB crystal.
 */

module usb_xtal_wrap (electrode1, electrode2, GND);

input electrode1, electrode2, GND;

xtal_4pin_pkg xtal (.pin_1(electrode1),
		    .pin_2(GND),
		    .pin_3(electrode2),
		    .pin_4(GND)
	);

endmodule