/*
 * This module encapsulates the mobile power domain buffers
 * in front of Calypso UART inputs.
 */

module calypso_uart_in (GND, VBAT, Vio,
			Host_TxD, Host_RTS, Host_DTR, Host_TxD2,
			RX_MODEM, CTS_MODEM, GPIO_DTR, RX_IRDA);

input GND, VBAT, Vio;
input Host_TxD, Host_RTS, Host_DTR, Host_TxD2;
output RX_MODEM, CTS_MODEM, GPIO_DTR, RX_IRDA;

/* U401 buffer common part */
logic_ic_common U401_common (.Vcc(Vio), .GND(GND));

/* bypass capacitor */
capacitor U401_bypass (Vio, GND);

/* buffer slots */
buffer_slot_3state Host_TxD_buffer  (.A(Host_TxD),  .nOE(GND), .Y(RX_MODEM));
buffer_slot_3state Host_RTS_buffer  (.A(Host_RTS),  .nOE(GND), .Y(CTS_MODEM));
buffer_slot_3state Host_DTR_buffer  (.A(Host_DTR),  .nOE(GND), .Y(GPIO_DTR));
buffer_slot_3state Host_TxD2_buffer (.A(Host_TxD2), .nOE(GND), .Y(RX_IRDA));

/* pull-ups to VBAT */
resistor Host_TxD_pullup  (Host_TxD,  VBAT);
resistor Host_DTR_pullup  (Host_DTR,  VBAT);
resistor Host_TxD2_pullup (Host_TxD2, VBAT);

/* pull-down to GND */
resistor Host_RTS_pulldown (Host_RTS, GND);

endmodule