FreeCalypso > hg > freecalypso-schem2

view venus/src/periph/Si9407AEY.v @ 98:3ab69117b09f default tip

Find changesets by keywords (author, files, the commit message), revision number or hash, or revset expression.
minnie/doc/Design-spec: finished in the first pass
author Mychaela Falconia <falcon@freecalypso.org>
date Sun, 01 Oct 2023 08:17:05 +0000
parents 74a89c0a6466
children
line wrap: on
line source

/*
 * This Verilog module encapsulates a MOSFET in a Si9407AEY-compatible
 * SOIC-8 footprint.
 */

module Si9407AEY (G, S, D);

input G, S;
output D;

/* instantiate the package; the mapping of signals to pins is defined here */

pkg_IC_8pin pkg (.pin_1(S),
		 .pin_2(S),
		 .pin_3(S),
		 .pin_4(G),
		 .pin_5(D),
		 .pin_6(D),
		 .pin_7(D),
		 .pin_8(D)
	);

endmodule