view venus/src/periph/bl_current_select.v @ 98:3ab69117b09f default tip

minnie/doc/Design-spec: finished in the first pass
author Mychaela Falconia <falcon@freecalypso.org>
date Sun, 01 Oct 2023 08:17:05 +0000
parents 9f5a3567d699
children
line wrap: on
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module bl_current_select (GND, Vio, BL_GPIO11, BL_GPIO12, SET);

input GND, Vio;
input BL_GPIO11, BL_GPIO12;
output SET;

wire buf_out_GPIO11, buf_out_GPIO12;

/* U403 buffer common part */
logic_ic_common U403_common (.Vcc(Vio), .GND(GND));

/* bypass capacitor */
capacitor U403_bypass (Vio, GND);

/* buffer slots */
buffer_slot_3state buf_GPIO11 (.A(Vio), .nOE(BL_GPIO11), .Y(buf_out_GPIO11));
buffer_slot_3state buf_GPIO12 (.A(Vio), .nOE(BL_GPIO12), .Y(buf_out_GPIO12));

/* MAX1916 current control resistors */
resistor R_fixed  (Vio, SET);
resistor R_GPIO11 (buf_out_GPIO11, SET);
resistor R_GPIO12 (buf_out_GPIO12, SET);

endmodule