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minnie/doc/Design-spec: finished in the first pass
author Mychaela Falconia <falcon@freecalypso.org>
date Sun, 01 Oct 2023 08:17:05 +0000
parents df6086f8788d
children
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# Mapping of Iota ABB signal connections from name to GGM package ball
# based on Table 2-3 on page 18 of TWL3025_SWRS021.pdf

#signal name	GGM package ball
ADIN1		B6
ADIN2		A6
ADIN3		C7
ADIN4		C6
AFC		J4
APC		K4
AUXI		G7
AUXON		K10
AUXOP		K9
BDLIM		F10
BDLIP		F9
BDLQM		E9
BDLQP		E10
BDR		J3
BDX		J2
BFSR		H3
BFSX		K2
BULIM		D10
BULIP		D9
BULQM		C9
BULQP		C10
CK13M		E4
CK32K		E2
DAC		H4
DBBSCK		F4
DBBSIO		E5
DBBSRST		G4
EARN		J10
EARP		J9
GNDA		G10
GNDAV		G6
GNDD		A3
GNDL1		B9
GNDL2		A9
HSMICBIAS	K8
HSMICP		K7
HSO		H9
IBIAS		B7
ICTL		D6
INT1		H6
INT2		E6
ITWAKEUP	D2
LEDA		B8
LEDB1		B10
LEDB2		A10
LEDC		C8
MICBIAS		J8
MICIN		H7
MICIP		J7
ON_nOFF		E3
PCHG		B5
PWON		F8
REFGND		A7
RESPWONz	D3
RPWON		F7
SIMCK		C4
SIMIO		B3
SIMRST		D4
TCK		D8
TDI		D7
TDO		E7
TDR		G3
TEN		H1
TEST3		J6
TEST4		F6
TESTRSTz	H8
TESTV		G8
TMS		E8
UDR		K5
UDX		J5
UEN		K6
UPR		C2
VBACKUP		E1
VBAT		A4
VBATS		C5
VCABB		G9
VCCS		D5
VCDBB		K1
VCHG		A5
VCIO1		A2
VCIO2		A1
VCK		K3
VCMEM		G2
VCRAM		F2
VDR		F5
VDX		H5
VFS		G5
VLMEM		F3
VLRTC		C3
VRABB		H10
VRDBB		J1
VREF		A8
VRIO1		B2
VRIO2		B1
VRMEM		G1
VRRAN		F1
VRRTC		D1
VRSIM		B4
VSDBB		H2
VXRTC		C1