/*
 * This structural Verilog module is the top level for FC Venus board.
 * It interconnects the two principal domains: mobile and USB.
 */

module board ();

wire GND, VBUS, VCHG;

wire Host_TxD, Host_RxD, Host_RTS, Host_CTS;
wire Host_DTR, Host_DCD, Host_RI, Host_TxD2, Host_RxD2;

wire RPWON, nTESTRESET;

/* mobile and USB domains */

mobile mob (.GND(GND),
	    .VCHG(VCHG),
	    .Host_TxD(Host_TxD),
	    .Host_RxD(Host_RxD),
	    .Host_RTS(Host_RTS),
	    .Host_CTS(Host_CTS),
	    .Host_DTR(Host_DTR),
	    .Host_DCD(Host_DCD),
	    .Host_RI(Host_RI),
	    .Host_TxD2(Host_TxD2),
	    .Host_RxD2(Host_RxD2),
	    .RPWON(RPWON),
	    .nTESTRESET(nTESTRESET)
	);

usb_domain usb (.GND(GND),
		.VBUS(VBUS),
		.Host_TxD(Host_TxD),
		.Host_RxD(Host_RxD),
		.Host_RTS(Host_RTS),
		.Host_CTS(Host_CTS),
		.Host_DTR(Host_DTR),
		.Host_DCD(Host_DCD),
		.Host_RI(Host_RI),
		.Host_TxD2(Host_TxD2),
		.Host_RxD2(Host_RxD2),
		.RPWON(RPWON),
		.nTESTRESET(nTESTRESET)
	);

/* charging control switch */

switch_2pin chg_switch (VBUS, VCHG);

/* pull-down resistors before and after the switch */

resistor VBUS_pulldown (VBUS, GND);
resistor VCHG_pulldown (VCHG, GND);

/* UART interface "rescue" header */

header_10pin uart_header (.pin_1(GND),
			  .pin_2(GND),
			  .pin_3(Host_RxD2),
			  .pin_4(Host_RxD),
			  .pin_5(Host_TxD2),
			  .pin_6(Host_TxD),
			  .pin_7(Host_DCD),
			  .pin_8(Host_CTS),
			  .pin_9(Host_DTR),
			  .pin_10(Host_RTS)
	);

endmodule