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minnie/doc/Design-spec: finished in the first pass
author Mychaela Falconia <falcon@freecalypso.org>
date Sun, 01 Oct 2023 08:17:05 +0000
parents 8f3df7a222f5
children
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/*
 * This Verilog module encapsulates the PCB footprint
 * for our 6.0 MHz USB crystal.
 */

module usb_xtal_wrap (electrode1, electrode2, GND);

input electrode1, electrode2, GND;

xtal_4pin_pkg xtal (.pin_1(electrode1),
		    .pin_2(GND),
		    .pin_3(electrode2),
		    .pin_4(GND)
	);

endmodule