FreeCalypso > hg > freecalypso-schem2
graph
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Venus src: jtag_if.v adapted from FCDEV3BSat, 20 Nov 2021 04:32:50 +0000, by Mychaela Falconia
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Venus src: SIM socket block capturedFri, 19 Nov 2021 20:59:14 +0000, by Mychaela Falconia
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Venus src: add 74LVC1G04 inverting buffer for SIM_CDFri, 19 Nov 2021 20:35:10 +0000, by Mychaela Falconia
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venus/src/periph/calypso_uart_in.v writtenFri, 19 Nov 2021 20:10:46 +0000, by Mychaela Falconia
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Venus primitives: add logic IC subpackagesFri, 19 Nov 2021 19:46:03 +0000, by Mychaela Falconia
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Venus MCL: add 74LVC125A for Calypso UART inputsFri, 19 Nov 2021 18:57:57 +0000, by Mychaela Falconia
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venus/src/periph/battery.v: adapted from FCDEV3BFri, 19 Nov 2021 06:48:25 +0000, by Mychaela Falconia
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venus/src/periph/sma_wrap.v: unchanged from FCDEV3BFri, 19 Nov 2021 06:44:53 +0000, by Mychaela Falconia
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Venus core: bring out SIM_CDFri, 19 Nov 2021 06:09:13 +0000, by Mychaela Falconia
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Venus: first version of Verilog for the Calypso coreFri, 19 Nov 2021 05:58:21 +0000, by Mychaela Falconia
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Venus primitives: add TRRS jackFri, 19 Nov 2021 03:47:49 +0000, by Mychaela Falconia
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Venus MCL: add audio jacksFri, 19 Nov 2021 03:44:51 +0000, by Mychaela Falconia