FreeCalypso > hg > freecalypso-schem2
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Verilog src: preparations for adding the keypadSat, 27 Nov 2021 04:43:53 +0000, by Mychaela Falconia
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MCL: preliminary part selection for keypad switchesSat, 27 Nov 2021 04:25:30 +0000, by Mychaela Falconia
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LCD subsystem integratedSat, 27 Nov 2021 02:46:19 +0000, by Mychaela Falconia
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progress toward LCD integrationSat, 27 Nov 2021 02:09:46 +0000, by Mychaela Falconia
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MAX1916.v and lcd_module.v from lunalcd2Sat, 27 Nov 2021 01:43:32 +0000, by Mychaela Falconia
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74LVC2G125 buffer for BL control captured at MCL levelSat, 27 Nov 2021 01:34:05 +0000, by Mychaela Falconia
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MCL and primitives: LCD and MAX1916 from lunalcd2Sat, 27 Nov 2021 01:09:05 +0000, by Mychaela Falconia
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add top READMESat, 27 Nov 2021 00:25:20 +0000, by Mychaela Falconia
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add missing bypass caps for mobile domain peripheralsFri, 26 Nov 2021 23:45:48 +0000, by Mychaela Falconia
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charging_circuit structural module contains no connections to GNDFri, 26 Nov 2021 23:32:00 +0000, by Mychaela Falconia
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use buffer_slot_od primitive for slots of 74LVC2G07Fri, 26 Nov 2021 23:18:12 +0000, by Mychaela Falconia
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implement USB domain load resistor as proposed in documentFri, 26 Nov 2021 23:08:09 +0000, by Mychaela Falconia
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venus/doc/USB-and-mobile-domains treatise writtenFri, 26 Nov 2021 23:02:19 +0000, by Mychaela Falconia
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venus/doc/MEMIF-fixed-2.8V: explanatory articleWed, 24 Nov 2021 18:14:11 +0000, by Mychaela Falconia