FreeCalypso > hg > freecalypso-schem2
graph
-
Venus MCL: add 74LVC125A for Calypso UART inputsFri, 19 Nov 2021 18:57:57 +0000, by Mychaela Falconia
-
venus/src/periph/battery.v: adapted from FCDEV3BFri, 19 Nov 2021 06:48:25 +0000, by Mychaela Falconia
-
venus/src/periph/sma_wrap.v: unchanged from FCDEV3BFri, 19 Nov 2021 06:44:53 +0000, by Mychaela Falconia
-
Venus core: bring out SIM_CDFri, 19 Nov 2021 06:09:13 +0000, by Mychaela Falconia
-
Venus: first version of Verilog for the Calypso coreFri, 19 Nov 2021 05:58:21 +0000, by Mychaela Falconia
-
Venus primitives: add TRRS jackFri, 19 Nov 2021 03:47:49 +0000, by Mychaela Falconia
-
Venus MCL: add audio jacksFri, 19 Nov 2021 03:44:51 +0000, by Mychaela Falconia