FreeCalypso > hg > freecalypso-schem2
graph
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eliminate R209 and tie Iota VLMEM directly to UPRMon, 22 Nov 2021 19:19:59 +0000, by Mychaela Falconia
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starpoints in core: commit to using pcb-rnd intnoconnMon, 22 Nov 2021 09:54:48 +0000, by Mychaela Falconia
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charging LED circuit capturedMon, 22 Nov 2021 03:25:55 +0000, by Mychaela Falconia
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intnoconn approach to charging current sense resistorMon, 22 Nov 2021 03:03:15 +0000, by Mychaela Falconia
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Venus src: charging circuit capturedSun, 21 Nov 2021 20:20:38 +0000, by Mychaela Falconia
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Venus MCL: use new ipc-diode.pinout, add SS34 for chargingSun, 21 Nov 2021 08:58:43 +0000, by Mychaela Falconia
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Venus MCL: add Q401 charging circuit MOSFETSun, 21 Nov 2021 08:40:13 +0000, by Mychaela Falconia
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venus/src/Makefile: generate bound.unetSun, 21 Nov 2021 03:14:56 +0000, by Mychaela Falconia
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Venus MCL: ready for first bindingSun, 21 Nov 2021 03:05:26 +0000, by Mychaela Falconia
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Venus MCL: first steps toward binding,Sun, 21 Nov 2021 02:14:49 +0000, by Mychaela Falconia
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Venus: reached the point of compiling sverp.unetSat, 20 Nov 2021 21:54:27 +0000, by Mychaela Falconia
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Venus: preliminary choice of slide switch part for charging controlSat, 20 Nov 2021 21:12:23 +0000, by Mychaela Falconia
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Venus src: USB domain capturedSat, 20 Nov 2021 19:44:59 +0000, by Mychaela Falconia
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venus/src/usb: building blocks from DUART28Sat, 20 Nov 2021 17:48:18 +0000, by Mychaela Falconia
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Venus primitives: additions for USBSat, 20 Nov 2021 09:10:02 +0000, by Mychaela Falconia
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Venus MCL: smaller package for USB EEPROMSat, 20 Nov 2021 08:32:54 +0000, by Mychaela Falconia
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Venus MCL: USB connector and ICs from DUART28Sat, 20 Nov 2021 06:19:00 +0000, by Mychaela Falconia
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venus/src/top/mobile.v writtenSat, 20 Nov 2021 05:45:37 +0000, by Mychaela Falconia
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Venus src: jtag_if.v adapted from FCDEV3BSat, 20 Nov 2021 04:32:50 +0000, by Mychaela Falconia
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Venus src: SIM socket block capturedFri, 19 Nov 2021 20:59:14 +0000, by Mychaela Falconia
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Venus src: add 74LVC1G04 inverting buffer for SIM_CDFri, 19 Nov 2021 20:35:10 +0000, by Mychaela Falconia
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venus/src/periph/calypso_uart_in.v writtenFri, 19 Nov 2021 20:10:46 +0000, by Mychaela Falconia
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Venus primitives: add logic IC subpackagesFri, 19 Nov 2021 19:46:03 +0000, by Mychaela Falconia
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Venus MCL: add 74LVC125A for Calypso UART inputsFri, 19 Nov 2021 18:57:57 +0000, by Mychaela Falconia
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venus/src/periph/battery.v: adapted from FCDEV3BFri, 19 Nov 2021 06:48:25 +0000, by Mychaela Falconia
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venus/src/periph/sma_wrap.v: unchanged from FCDEV3BFri, 19 Nov 2021 06:44:53 +0000, by Mychaela Falconia
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Venus core: bring out SIM_CDFri, 19 Nov 2021 06:09:13 +0000, by Mychaela Falconia
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Venus: first version of Verilog for the Calypso coreFri, 19 Nov 2021 05:58:21 +0000, by Mychaela Falconia