FreeCalypso > hg > freecalypso-schem2
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MCL: assign value to all capacitorsThu, 02 Dec 2021 05:53:13 +0000, by Mychaela Falconia
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change USB 6.0 MHz crystal to a smaller partThu, 02 Dec 2021 01:35:34 +0000, by Mychaela Falconia
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change SMA connector from SMT to THThu, 02 Dec 2021 00:36:28 +0000, by Mychaela Falconia
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venus/src/Makefile: unet-bind -c to check completenessWed, 01 Dec 2021 21:47:20 +0000, by Mychaela Falconia
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add manual RESET buttonWed, 01 Dec 2021 21:45:42 +0000, by Mychaela Falconia
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buzzer circuit implementedWed, 01 Dec 2021 20:22:47 +0000, by Mychaela Falconia
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clamping diode pair for the buzzer driving circuitWed, 01 Dec 2021 19:26:29 +0000, by Mychaela Falconia
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transistor for driving the buzzerWed, 01 Dec 2021 18:39:48 +0000, by Mychaela Falconia
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buzzer component nailed downWed, 01 Dec 2021 06:50:25 +0000, by Mychaela Falconia
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loudspeaker block implementedWed, 01 Dec 2021 04:08:35 +0000, by Mychaela Falconia
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HSO audio channel implementedWed, 01 Dec 2021 03:26:15 +0000, by Mychaela Falconia
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main audio channel implementedWed, 01 Dec 2021 02:22:39 +0000, by Mychaela Falconia
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VSP sniff tap implementedSat, 27 Nov 2021 20:43:23 +0000, by Mychaela Falconia
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add VBAT tap for calibration measurementsSat, 27 Nov 2021 20:01:56 +0000, by Mychaela Falconia
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LPG and PWL LEDs implementedSat, 27 Nov 2021 19:46:01 +0000, by Mychaela Falconia
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MCL: prebiased transistor pair partsSat, 27 Nov 2021 19:16:58 +0000, by Mychaela Falconia
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ON_nOFF indicator LED implementedSat, 27 Nov 2021 18:34:05 +0000, by Mychaela Falconia
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keypad initial implementationSat, 27 Nov 2021 07:03:14 +0000, by Mychaela Falconia
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Verilog src: preparations for adding the keypadSat, 27 Nov 2021 04:43:53 +0000, by Mychaela Falconia
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MCL: preliminary part selection for keypad switchesSat, 27 Nov 2021 04:25:30 +0000, by Mychaela Falconia
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LCD subsystem integratedSat, 27 Nov 2021 02:46:19 +0000, by Mychaela Falconia
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progress toward LCD integrationSat, 27 Nov 2021 02:09:46 +0000, by Mychaela Falconia
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MAX1916.v and lcd_module.v from lunalcd2Sat, 27 Nov 2021 01:43:32 +0000, by Mychaela Falconia
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74LVC2G125 buffer for BL control captured at MCL levelSat, 27 Nov 2021 01:34:05 +0000, by Mychaela Falconia
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MCL and primitives: LCD and MAX1916 from lunalcd2Sat, 27 Nov 2021 01:09:05 +0000, by Mychaela Falconia
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add top READMESat, 27 Nov 2021 00:25:20 +0000, by Mychaela Falconia
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add missing bypass caps for mobile domain peripheralsFri, 26 Nov 2021 23:45:48 +0000, by Mychaela Falconia
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charging_circuit structural module contains no connections to GNDFri, 26 Nov 2021 23:32:00 +0000, by Mychaela Falconia
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use buffer_slot_od primitive for slots of 74LVC2G07Fri, 26 Nov 2021 23:18:12 +0000, by Mychaela Falconia
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implement USB domain load resistor as proposed in documentFri, 26 Nov 2021 23:08:09 +0000, by Mychaela Falconia
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venus/doc/USB-and-mobile-domains treatise writtenFri, 26 Nov 2021 23:02:19 +0000, by Mychaela Falconia
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venus/doc/MEMIF-fixed-2.8V: explanatory articleWed, 24 Nov 2021 18:14:11 +0000, by Mychaela Falconia
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eliminate R209 and tie Iota VLMEM directly to UPRMon, 22 Nov 2021 19:19:59 +0000, by Mychaela Falconia
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starpoints in core: commit to using pcb-rnd intnoconnMon, 22 Nov 2021 09:54:48 +0000, by Mychaela Falconia
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charging LED circuit capturedMon, 22 Nov 2021 03:25:55 +0000, by Mychaela Falconia
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intnoconn approach to charging current sense resistorMon, 22 Nov 2021 03:03:15 +0000, by Mychaela Falconia
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Venus src: charging circuit capturedSun, 21 Nov 2021 20:20:38 +0000, by Mychaela Falconia
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Venus MCL: use new ipc-diode.pinout, add SS34 for chargingSun, 21 Nov 2021 08:58:43 +0000, by Mychaela Falconia
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Venus MCL: add Q401 charging circuit MOSFETSun, 21 Nov 2021 08:40:13 +0000, by Mychaela Falconia
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venus/src/Makefile: generate bound.unetSun, 21 Nov 2021 03:14:56 +0000, by Mychaela Falconia
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Venus MCL: ready for first bindingSun, 21 Nov 2021 03:05:26 +0000, by Mychaela Falconia
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Venus MCL: first steps toward binding,Sun, 21 Nov 2021 02:14:49 +0000, by Mychaela Falconia
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Venus: reached the point of compiling sverp.unetSat, 20 Nov 2021 21:54:27 +0000, by Mychaela Falconia
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Venus: preliminary choice of slide switch part for charging controlSat, 20 Nov 2021 21:12:23 +0000, by Mychaela Falconia
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Venus src: USB domain capturedSat, 20 Nov 2021 19:44:59 +0000, by Mychaela Falconia
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venus/src/usb: building blocks from DUART28Sat, 20 Nov 2021 17:48:18 +0000, by Mychaela Falconia
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Venus primitives: additions for USBSat, 20 Nov 2021 09:10:02 +0000, by Mychaela Falconia
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Venus MCL: smaller package for USB EEPROMSat, 20 Nov 2021 08:32:54 +0000, by Mychaela Falconia
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Venus MCL: USB connector and ICs from DUART28Sat, 20 Nov 2021 06:19:00 +0000, by Mychaela Falconia
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venus/src/top/mobile.v writtenSat, 20 Nov 2021 05:45:37 +0000, by Mychaela Falconia
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Venus src: jtag_if.v adapted from FCDEV3BSat, 20 Nov 2021 04:32:50 +0000, by Mychaela Falconia
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Venus src: SIM socket block capturedFri, 19 Nov 2021 20:59:14 +0000, by Mychaela Falconia
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Venus src: add 74LVC1G04 inverting buffer for SIM_CDFri, 19 Nov 2021 20:35:10 +0000, by Mychaela Falconia
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venus/src/periph/calypso_uart_in.v writtenFri, 19 Nov 2021 20:10:46 +0000, by Mychaela Falconia
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Venus primitives: add logic IC subpackagesFri, 19 Nov 2021 19:46:03 +0000, by Mychaela Falconia
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Venus MCL: add 74LVC125A for Calypso UART inputsFri, 19 Nov 2021 18:57:57 +0000, by Mychaela Falconia
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venus/src/periph/battery.v: adapted from FCDEV3BFri, 19 Nov 2021 06:48:25 +0000, by Mychaela Falconia
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venus/src/periph/sma_wrap.v: unchanged from FCDEV3BFri, 19 Nov 2021 06:44:53 +0000, by Mychaela Falconia
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Venus core: bring out SIM_CDFri, 19 Nov 2021 06:09:13 +0000, by Mychaela Falconia
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Venus: first version of Verilog for the Calypso coreFri, 19 Nov 2021 05:58:21 +0000, by Mychaela Falconia
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Venus primitives: add TRRS jackFri, 19 Nov 2021 03:47:49 +0000, by Mychaela Falconia
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Venus MCL: add audio jacksFri, 19 Nov 2021 03:44:51 +0000, by Mychaela Falconia
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Venus primitives file startedFri, 19 Nov 2021 03:07:48 +0000, by Mychaela Falconia
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Venus MCL: add LEDsFri, 19 Nov 2021 01:43:41 +0000, by Mychaela Falconia