FreeCalypso > hg > freecalypso-schem2

log venus/src/core/baseband.v @ 94:4502eec1e805

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Sat, 11 Dec 2021 05:38:21 +0000 Mychaela Falconia change VSP tap header to 6 pins, add CLK13M
Sat, 11 Dec 2021 04:48:30 +0000 Mychaela Falconia add RTC domain test points
Fri, 10 Dec 2021 06:20:19 +0000 Mychaela Falconia add 74AXP1T34 buffer for flash reset
Sat, 27 Nov 2021 20:43:23 +0000 Mychaela Falconia VSP sniff tap implemented
Fri, 19 Nov 2021 06:09:13 +0000 Mychaela Falconia Venus core: bring out SIM_CD
Fri, 19 Nov 2021 05:58:21 +0000 Mychaela Falconia Venus: first version of Verilog for the Calypso core
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