FreeCalypso > hg > freecalypso-schem2
log venus/src/MCL @ 48:d55824058cfc
| age | author | description |
|---|---|---|
| Sat, 27 Nov 2021 02:46:19 +0000 | Mychaela Falconia | LCD subsystem integrated |
| Sat, 27 Nov 2021 01:34:05 +0000 | Mychaela Falconia | 74LVC2G125 buffer for BL control captured at MCL level |
| Sat, 27 Nov 2021 01:09:05 +0000 | Mychaela Falconia | MCL and primitives: LCD and MAX1916 from lunalcd2 |
| Fri, 26 Nov 2021 23:45:48 +0000 | Mychaela Falconia | add missing bypass caps for mobile domain peripherals |
| Fri, 26 Nov 2021 23:08:09 +0000 | Mychaela Falconia | implement USB domain load resistor as proposed in document |
| Mon, 22 Nov 2021 19:19:59 +0000 | Mychaela Falconia | eliminate R209 and tie Iota VLMEM directly to UPR |
| Mon, 22 Nov 2021 09:54:48 +0000 | Mychaela Falconia | starpoints in core: commit to using pcb-rnd intnoconn |