# HG changeset patch
# User Mychaela Falconia <falcon@freecalypso.org>
# Date 1637302153 0
# Node ID 5ee03a306da3f1738bfc99d47bc6f0fd8a9c6b71
# Parent  3ed0f7a9c489024d87488223f8ba4702b41b41c7
Venus core: bring out SIM_CD

diff -r 3ed0f7a9c489 -r 5ee03a306da3 venus/src/core/baseband.v
--- a/venus/src/core/baseband.v	Fri Nov 19 05:58:21 2021 +0000
+++ b/venus/src/core/baseband.v	Fri Nov 19 06:09:13 2021 +0000
@@ -21,7 +21,7 @@
 		 MICBIAS, MICIN, MICIP,
 		 LED_A, LED_B, LED_C,
 		 ICTL, PCHG, VBATS, VCCS, VCHG,
-		 SIM_IO, SIM_CLK, SIM_RST,
+		 SIM_IO, SIM_CLK, SIM_RST, SIM_CD,
 		 Analog_IM, Analog_IP, Analog_QM, Analog_QP, AFC, APC,
 		 TCXOEN, RFEN, TSPCLK, TSPDO, TSPEN_Rita, TSPACT);
 
@@ -76,6 +76,7 @@
 
 output SIM_CLK, SIM_RST;
 inout SIM_IO;
+input SIM_CD;
 
 inout Analog_IM, Analog_IP, Analog_QM, Analog_QP;
 output AFC, APC;
@@ -185,7 +186,8 @@
 		.MCUEN2_IO13(GPIO13),
 		.SIM_IO(DBBSIO),
 		.SIM_CLK(DBBSCLK),
-		.SIM_RST(DBBSRST)
+		.SIM_RST(DBBSRST),
+		.SIM_CD(SIM_CD)
 	);
 
 abb_block abb ( .GND(GND),
diff -r 3ed0f7a9c489 -r 5ee03a306da3 venus/src/core/core.v
--- a/venus/src/core/core.v	Fri Nov 19 05:58:21 2021 +0000
+++ b/venus/src/core/core.v	Fri Nov 19 06:09:13 2021 +0000
@@ -20,7 +20,7 @@
 	     MICBIAS, MICIN, MICIP,
 	     LED_A, LED_B, LED_C,
 	     ICTL, PCHG, VBATS, VCCS, VCHG,
-	     SIM_IO, SIM_CLK, SIM_RST, ANTENNA);
+	     SIM_IO, SIM_CLK, SIM_RST, SIM_CD, ANTENNA);
 
 input GND, VBAT1, VBAT2, VBAT3;
 output VSIM, Vio;
@@ -71,6 +71,7 @@
 
 output SIM_CLK, SIM_RST;
 inout SIM_IO;
+input SIM_CD;
 inout ANTENNA;
 
 /* wires between baseband and RF */
@@ -175,6 +176,7 @@
 	     .SIM_IO(SIM_IO),
 	     .SIM_CLK(SIM_CLK),
 	     .SIM_RST(SIM_RST),
+	     .SIM_CD(SIM_CD),
 	     .Analog_IM(Analog_IM),
 	     .Analog_IP(Analog_IP),
 	     .Analog_QM(Analog_QM),
diff -r 3ed0f7a9c489 -r 5ee03a306da3 venus/src/core/dbb_block.v
--- a/venus/src/core/dbb_block.v	Fri Nov 19 05:58:21 2021 +0000
+++ b/venus/src/core/dbb_block.v	Fri Nov 19 06:09:13 2021 +0000
@@ -3,7 +3,7 @@
  *
  * - star points and bypass capacitors for the powering arrangement;
  * - the 32 kHz xtal circuit with its special ground;
- * - nIBOOT, IDDQ, SIM_CD and SIM_PWCTRL tie-offs;
+ * - nIBOOT, IDDQ and SIM_PWCTRL tie-offs;
  * - nBSCAN and nEMU[1:0] no-connects.
  *
  * All other Calypso signals are passed through untouched.
@@ -24,7 +24,7 @@
 		  BFSR, BDR, BFSX, BDX, BCLKX_IO6, BCLKR_ARMCLK,
 		  VDX, VDR, VFSRX, VCLKRX,
 		  MCUDI, MCUDO, MCUEN0, MCUEN1_IO8, MCUEN2_IO13,
-		  SIM_IO, SIM_CLK, SIM_RST);
+		  SIM_IO, SIM_CLK, SIM_RST, SIM_CD);
 
 input GND, Vdbb, Vio, Vflash, Vrtc;
 
@@ -78,6 +78,7 @@
 
 inout SIM_IO;
 output SIM_CLK, SIM_RST;
+input SIM_CD;
 
 /* nets inside this module */
 wire SIM_PWCTRL;
@@ -179,7 +180,7 @@
 			.SIM_IO(SIM_IO),
 			.SIM_CLK(SIM_CLK),
 			.SIM_RST(SIM_RST),
-			.SIM_CD(Vio),
+			.SIM_CD(SIM_CD),
 			.SIM_PWCTRL_IO5(SIM_PWCTRL));
 
 /* power bypass caps, absolutely unchanged from Leonardo */