# HG changeset patch
# User Mychaela Falconia <falcon@freecalypso.org>
# Date 1637484013 0
# Node ID 74a89c0a64666c34d65475085604da078183d768
# Parent  d03d6dcd194c944a305f3644eb2d9083ae14140c
Venus MCL: add Q401 charging circuit MOSFET

diff -r d03d6dcd194c -r 74a89c0a6466 venus/src/MCL
--- a/venus/src/MCL	Sun Nov 21 03:14:56 2021 +0000
+++ b/venus/src/MCL	Sun Nov 21 08:40:13 2021 +0000
@@ -696,6 +696,13 @@
  vendor=Digi-Key
  vendor_part_number=SI1032R-T1-GE3CT-ND
 
+# P-channel power MOSFET for the charging circuit
+# specific part TBD, needs to be footprint-compatible with Si9407AEY,
+# as shown in TI's APN0 document
+Q401:
+ footprint=SO8
+ npins=8
+
 Q600:
  part=EMB9
  slotmap=slotmap/Q600
diff -r d03d6dcd194c -r 74a89c0a6466 venus/src/Makefile
--- a/venus/src/Makefile	Sun Nov 21 03:14:56 2021 +0000
+++ b/venus/src/Makefile	Sun Nov 21 08:40:13 2021 +0000
@@ -8,9 +8,9 @@
 	core/rfmatch_rita2pa_hb.v core/rfmatch_rita2pa_lb.v \
 	core/rita_rf_chip.v core/rita_vcxo_int.v core/rita_wrap.v \
 	core/xtal_32khz_wrap.v \
-	periph/battery.v periph/calypso_uart_in.v periph/inv_buffer_74LVC1G04.v\
-	periph/jtag_if.v periph/sim_socket_block.v periph/sim_socket_wrap.v \
-	periph/sma_wrap.v \
+	periph/Si9407AEY.v periph/battery.v periph/calypso_uart_in.v \
+	periph/inv_buffer_74LVC1G04.v periph/jtag_if.v \
+	periph/sim_socket_block.v periph/sim_socket_wrap.v periph/sma_wrap.v \
 	top/board.v top/mobile.v \
 	usb/FT2232D_block.v usb/FT2232D_chip.v usb/eeprom_93Cx6_16bit.v \
 	usb/regulator_ic.v usb/regulator_with_caps.v usb/usb_conn.v \
diff -r d03d6dcd194c -r 74a89c0a6466 venus/src/periph/Si9407AEY.v
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/venus/src/periph/Si9407AEY.v	Sun Nov 21 08:40:13 2021 +0000
@@ -0,0 +1,23 @@
+/*
+ * This Verilog module encapsulates a MOSFET in a Si9407AEY-compatible
+ * SOIC-8 footprint.
+ */
+
+module Si9407AEY (G, S, D);
+
+input G, S;
+output D;
+
+/* instantiate the package; the mapping of signals to pins is defined here */
+
+pkg_IC_8pin pkg (.pin_1(S),
+		 .pin_2(S),
+		 .pin_3(S),
+		 .pin_4(G),
+		 .pin_5(D),
+		 .pin_6(D),
+		 .pin_7(D),
+		 .pin_8(D)
+	);
+
+endmodule