# HG changeset patch
# User Mychaela Falconia <falcon@freecalypso.org>
# Date 1639115938 0
# Node ID 93b238ad7d6e3df5d6ac18265f3a4f575b7eb1d2
# Parent  beb6519a3be51c960799035e40f0030a7a364933
first preparations for changing flash+RAM MCP to S71PL129N

diff -r beb6519a3be5 -r 93b238ad7d6e venus/src/Makefile
--- a/venus/src/Makefile	Wed Dec 08 07:36:45 2021 +0000
+++ b/venus/src/Makefile	Fri Dec 10 05:58:58 2021 +0000
@@ -1,8 +1,8 @@
-VSRCS=	core/M034F.v core/RF3166.v core/S71PL064J.v core/abb_block.v \
-	core/abb_rc_network.v core/baseband.v core/calypso_179ghh.v \
-	core/clock_rf2dbb.v core/core.v core/dbb_block.v \
-	core/int_vcxo_passive.v core/iota_100ggm.v core/memory.v \
-	core/rf_fem_block.v core/rf_pa_block.v core/rf_section.v \
+VSRCS=	core/M034F.v core/RF3166.v core/S71PL064J.v core/S71PL129N.v \
+	core/abb_block.v core/abb_rc_network.v core/baseband.v \
+	core/buffer_74AXP1T34.v core/calypso_179ghh.v core/clock_rf2dbb.v \
+	core/core.v core/dbb_block.v core/int_vcxo_passive.v core/iota_100ggm.v\
+	core/memory.v core/rf_fem_block.v core/rf_pa_block.v core/rf_section.v \
 	core/rfmatch_fem2rita_dcs.v core/rfmatch_fem2rita_low.v \
 	core/rfmatch_fem2rita_pcs.v core/rfmatch_pa2fem_pi.v \
 	core/rfmatch_rita2pa_hb.v core/rfmatch_rita2pa_lb.v \
diff -r beb6519a3be5 -r 93b238ad7d6e venus/src/core/S71PL129N.v
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/venus/src/core/S71PL129N.v	Fri Dec 10 05:58:58 2021 +0000
@@ -0,0 +1,83 @@
+module S71PL129N (Flash_Vcc, RAM_Vcc, Vss,
+		  A, DQ, OE, WE,
+		  Flash_CE1, Flash_CE2, Flash_RST,
+		  Flash_WP_ACC, Flash_ready_busy,
+		  RAM_CE_actlow, RAM_CE_acthigh, RAM_UB, RAM_LB);
+
+input Flash_Vcc, RAM_Vcc, Vss;
+input [21:0] A;
+inout [15:0] DQ;
+input OE, WE;
+input Flash_CE1, Flash_CE2, Flash_RST, Flash_WP_ACC;
+output Flash_ready_busy;
+input RAM_CE_actlow, RAM_CE_acthigh, RAM_UB, RAM_LB;
+
+/* instantiate the package; the mapping of signals to balls is defined here */
+
+pkg_TLA064 pkg (.A1(),		/* no connect */
+		.A10(),		/* ditto */
+		.B5(),		/* "" */
+		.B6(),
+		.C3(A[7]),
+		.C4(RAM_LB),
+		.C5(Flash_WP_ACC),
+		.C6(WE),
+		.C7(A[8]),
+		.C8(A[11]),
+		.D2(A[3]),
+		.D3(A[6]),
+		.D4(RAM_UB),
+		.D5(Flash_RST),
+		.D6(RAM_CE_acthigh),
+		.D7(A[19]),
+		.D8(A[12]),
+		.D9(A[15]),
+		.E2(A[2]),
+		.E3(A[5]),
+		.E4(A[18]),
+		.E5(Flash_ready_busy),
+		.E6(A[20]),
+		.E7(A[9]),
+		.E8(A[13]),
+		.E9(A[21]),
+		.F2(A[1]),
+		.F3(A[4]),
+		.F4(A[17]),
+		.F7(A[10]),
+		.F8(A[14]),
+		.F9(Flash_CE2),
+		.G2(A[0]),
+		.G3(Vss),
+		.G4(DQ[1]),
+		.G7(DQ[6]),
+		.G8(),		/* no connect */
+		.G9(A[16]),
+		.H2(Flash_CE1),
+		.H3(OE),
+		.H4(DQ[9]),
+		.H5(DQ[3]),
+		.H6(DQ[4]),
+		.H7(DQ[13]),
+		.H8(DQ[15]),
+		.H9(),		/* no connect */
+		.J2(RAM_CE_actlow),
+		.J3(DQ[0]),
+		.J4(DQ[10]),
+		.J5(Flash_Vcc),
+		.J6(RAM_Vcc),
+		.J7(DQ[12]),
+		.J8(DQ[7]),
+		.J9(Vss),
+		.K3(DQ[8]),
+		.K4(DQ[2]),
+		.K5(DQ[11]),
+		.K6(),		/* no connect */
+		.K7(DQ[5]),
+		.K8(DQ[14]),
+		.L5(),		/* no connect */
+		.L6(),		/* ditto */
+		.M1(),		/* "" */
+		.M10()
+	);
+
+endmodule
diff -r beb6519a3be5 -r 93b238ad7d6e venus/src/core/buffer_74AXP1T34.v
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/venus/src/core/buffer_74AXP1T34.v	Fri Dec 10 05:58:58 2021 +0000
@@ -0,0 +1,17 @@
+module buffer_74AXP1T34 (GND, Vcci, Vcco, A, Y);
+
+input GND, Vcci, Vcco;
+input A;
+output Y;
+
+/* instantiate the package; the mapping of signals to pins is defined here */
+
+pkg_XSON6 pkg  (.pin_1(Vcci),
+		.pin_2(A),
+		.pin_3(GND),
+		.pin_4(Y),
+		.pin_5(),	/* no connect */
+		.pin_6(Vcco)
+	);
+
+endmodule