FreeCalypso > hg > freecalypso-schem2
changeset 93:0a26e46b2fc2
change VSP tap header to 6 pins, add CLK13M
author | Mychaela Falconia <falcon@freecalypso.org> |
---|---|
date | Sat, 11 Dec 2021 05:38:21 +0000 |
parents | 148fab6e07e3 |
children | 4502eec1e805 |
files | venus/src/MCL venus/src/core/baseband.v venus/src/primitives |
diffstat | 3 files changed, 12 insertions(+), 9 deletions(-) [+] |
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--- a/venus/src/MCL Sat Dec 11 04:48:30 2021 +0000 +++ b/venus/src/MCL Sat Dec 11 05:38:21 2021 +0000 @@ -794,13 +794,12 @@ # VSP internal interface tap J404: hier=mob.core.bb.VSP_tap - footprint=JUMPER5 - description=Header, 0.100", single row, 5 posts + description=Header, 0.100", dual row, 6 posts manufacturer=Molex - manufacturer_part_number=0901200125 + manufacturer_part_number=0901310123 vendor=Digi-Key - vendor_part_number=WM8075-ND - npins=5 + vendor_part_number=WM50035-06-ND + npins=6 # VBAT tap for calibration measurements J405:
--- a/venus/src/core/baseband.v Sat Dec 11 04:48:30 2021 +0000 +++ b/venus/src/core/baseband.v Sat Dec 11 05:38:21 2021 +0000 @@ -267,12 +267,16 @@ /* there needs to be a pull-down resistor on the MCUDI/UDX net */ resistor R216 (USP_abb2dbb_data, GND); -/* VSP tap header */ -header_5pin VSP_tap ( .pin_1(VSP_clock), +/* + * VSP tap header - the pinout is preliminary, PCB layout engineer + * should feel free to change it for best layout. + */ +header_6pin VSP_tap ( .pin_1(VSP_clock), .pin_2(VSP_UL_data), .pin_3(VSP_DL_data), .pin_4(VSP_sync), - .pin_5(GND) + .pin_5(CLK13M_OUT), + .pin_6(GND) ); /* RTC domain test points */