changeset 15:42a02257d457

venus/src/periph/calypso_uart_in.v written
author Mychaela Falconia <falcon@freecalypso.org>
date Fri, 19 Nov 2021 20:10:46 +0000
parents ff784add0889
children 3d5c40988a6b
files venus/src/periph/calypso_uart_in.v
diffstat 1 files changed, 31 insertions(+), 0 deletions(-) [+]
line wrap: on
line diff
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/venus/src/periph/calypso_uart_in.v	Fri Nov 19 20:10:46 2021 +0000
@@ -0,0 +1,31 @@
+/*
+ * This module encapsulates the mobile power domain buffers
+ * in front of Calypso UART inputs.
+ */
+
+module calypso_uart_in (GND, VBAT, Vio,
+			Host_TxD, Host_RTS, Host_DTR, Host_TxD2,
+			RX_MODEM, CTS_MODEM, GPIO_DTR, RX_IRDA);
+
+input GND, VBAT, Vio;
+input Host_TxD, Host_RTS, Host_DTR, Host_TxD2;
+output RX_MODEM, CTS_MODEM, GPIO_DTR, RX_IRDA;
+
+/* U401 buffer common part */
+logic_ic_common U401_common (.Vcc(Vio), .GND(GND));
+
+/* buffer slots */
+buffer_slot_3state Host_TxD_buffer  (.A(Host_TxD),  .Y(RX_MODEM));
+buffer_slot_3state Host_RTS_buffer  (.A(Host_RTS),  .Y(CTS_MODEM));
+buffer_slot_3state Host_DTR_buffer  (.A(Host_DTR),  .Y(GPIO_DTR));
+buffer_slot_3state Host_TxD2_buffer (.A(Host_TxD2), .Y(RX_IRDA));
+
+/* pull-ups to VBAT */
+resistor Host_TxD_pullup  (Host_TxD,  VBAT);
+resistor Host_DTR_pullup  (Host_DTR,  VBAT);
+resistor Host_TxD2_pullup (Host_TxD2, VBAT);
+
+/* pull-down to GND */
+resistor Host_RTS_pulldown (Host_RTS, GND);
+
+endmodule