FreeCalypso > hg > freecalypso-schem2
changeset 26:4baae6215619
Venus: reached the point of compiling sverp.unet
| author | Mychaela Falconia <falcon@freecalypso.org> |
|---|---|
| date | Sat, 20 Nov 2021 21:54:27 +0000 |
| parents | 250fd753c0c5 |
| children | bd28df303f7b |
| files | .hgignore venus/src/Makefile venus/src/periph/calypso_uart_in.v venus/src/sympath venus/src/top/board.v |
| diffstat | 5 files changed, 99 insertions(+), 4 deletions(-) [+] |
line wrap: on
line diff
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/.hgignore Sat Nov 20 21:54:27 2021 +0000 @@ -0,0 +1,11 @@ +syntax: regexp + +\.asc$ +\.csv$ +\.donl$ +\.eco$ +\.section$ +\.txt$ +\.unet$ +\.ps$ +\.pdf$
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/venus/src/Makefile Sat Nov 20 21:54:27 2021 +0000 @@ -0,0 +1,27 @@ +VSRCS= core/M034F.v core/RF3166.v core/S71PL064J.v core/abb_block.v \ + core/abb_rc_network.v core/baseband.v core/calypso_179ghh.v \ + core/clock_rf2dbb.v core/core.v core/dbb_block.v \ + core/int_vcxo_passive.v core/iota_100ggm.v core/memory.v \ + core/rf_fem_block.v core/rf_pa_block.v core/rf_section.v \ + core/rfmatch_fem2rita_dcs.v core/rfmatch_fem2rita_low.v \ + core/rfmatch_fem2rita_pcs.v core/rfmatch_pa2fem_pi.v \ + core/rfmatch_rita2pa_hb.v core/rfmatch_rita2pa_lb.v \ + core/rita_rf_chip.v core/rita_vcxo_int.v core/rita_wrap.v \ + core/xtal_32khz_wrap.v \ + periph/battery.v periph/calypso_uart_in.v periph/inv_buffer_74LVC1G04.v\ + periph/jtag_if.v periph/sim_socket_block.v periph/sim_socket_wrap.v \ + periph/sma_wrap.v \ + top/board.v top/mobile.v \ + usb/FT2232D_block.v usb/FT2232D_chip.v usb/eeprom_93Cx6_16bit.v \ + usb/regulator_ic.v usb/regulator_with_caps.v usb/usb_conn.v \ + usb/usb_core.v usb/usb_domain.v usb/usb_domain_bctl.v \ + usb/usb_domain_buf.v +NETS= sverp.unet + +all: ${NETS} + +sverp.unet: ${VSRCS} primitives Makefile + ueda-sverp -o $@ ${VSRCS} + +clean: + rm -f *.unet *.txt *.csv
--- a/venus/src/periph/calypso_uart_in.v Sat Nov 20 21:12:23 2021 +0000 +++ b/venus/src/periph/calypso_uart_in.v Sat Nov 20 21:54:27 2021 +0000 @@ -15,10 +15,10 @@ logic_ic_common U401_common (.Vcc(Vio), .GND(GND)); /* buffer slots */ -buffer_slot_3state Host_TxD_buffer (.A(Host_TxD), .Y(RX_MODEM)); -buffer_slot_3state Host_RTS_buffer (.A(Host_RTS), .Y(CTS_MODEM)); -buffer_slot_3state Host_DTR_buffer (.A(Host_DTR), .Y(GPIO_DTR)); -buffer_slot_3state Host_TxD2_buffer (.A(Host_TxD2), .Y(RX_IRDA)); +buffer_slot_3state Host_TxD_buffer (.A(Host_TxD), .nOE(GND), .Y(RX_MODEM)); +buffer_slot_3state Host_RTS_buffer (.A(Host_RTS), .nOE(GND), .Y(CTS_MODEM)); +buffer_slot_3state Host_DTR_buffer (.A(Host_DTR), .nOE(GND), .Y(GPIO_DTR)); +buffer_slot_3state Host_TxD2_buffer (.A(Host_TxD2), .nOE(GND), .Y(RX_IRDA)); /* pull-ups to VBAT */ resistor Host_TxD_pullup (Host_TxD, VBAT);
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/venus/src/sympath Sat Nov 20 21:54:27 2021 +0000 @@ -0,0 +1,1 @@ +./pinouts
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/venus/src/top/board.v Sat Nov 20 21:54:27 2021 +0000 @@ -0,0 +1,56 @@ +/* + * This structural Verilog module is the top level for FC Venus board. + * It interconnects the two principal domains: mobile and USB. + */ + +module board (); + +wire GND, VBUS, VCHG; + +wire Host_TxD, Host_RxD, Host_RTS, Host_CTS; +wire Host_DTR, Host_DCD, Host_RI, Host_TxD2, Host_RxD2; + +wire RPWON, nTESTRESET; + +/* mobile and USB domains */ + +mobile mob (.GND(GND), + .VCHG(VCHG), + .Host_TxD(Host_TxD), + .Host_RxD(Host_RxD), + .Host_RTS(Host_RTS), + .Host_CTS(Host_CTS), + .Host_DTR(Host_DTR), + .Host_DCD(Host_DCD), + .Host_RI(Host_RI), + .Host_TxD2(Host_TxD2), + .Host_RxD2(Host_RxD2), + .RPWON(RPWON), + .nTESTRESET(nTESTRESET) + ); + +usb_domain usb (.GND(GND), + .VBUS(VBUS), + .Host_TxD(Host_TxD), + .Host_RxD(Host_RxD), + .Host_RTS(Host_RTS), + .Host_CTS(Host_CTS), + .Host_DTR(Host_DTR), + .Host_DCD(Host_DCD), + .Host_RI(Host_RI), + .Host_TxD2(Host_TxD2), + .Host_RxD2(Host_RxD2), + .RPWON(RPWON), + .nTESTRESET(nTESTRESET) + ); + +/* charging control switch */ + +switch_2pin chg_switch (VBUS, VCHG); + +/* pull-down resistors before and after the switch */ + +resistor VBUS_pulldown (VBUS, GND); +resistor VCHG_pulldown (VCHG, GND); + +endmodule