FreeCalypso > hg > freecalypso-schem2
changeset 36:c1256c8757c3
eliminate R209 and tie Iota VLMEM directly to UPR
We already eliminated R210 (VLMEM pull-down option) earlier, because
our simplified LCD power supply and reset line wiring is incompatible
with 1.8V MEMIF. But with VLMEM always needing to be high, a pull-up
resistor offers no advantage over a direct tie to UPR, so let's
eliminate the superfluous resistor.
| author | Mychaela Falconia <falcon@freecalypso.org> |
|---|---|
| date | Mon, 22 Nov 2021 19:19:59 +0000 |
| parents | 971c05950675 |
| children | 9c2f913fa5cf |
| files | venus/src/MCL venus/src/core/abb_block.v |
| diffstat | 2 files changed, 3 insertions(+), 15 deletions(-) [+] |
line wrap: on
line diff
--- a/venus/src/MCL Mon Nov 22 09:54:48 2021 +0000 +++ b/venus/src/MCL Mon Nov 22 19:19:59 2021 +0000 @@ -787,12 +787,6 @@ footprint=0402 npins=2 -R209: - # pull-up of Iota VLMEM to UPR - hier=mob.core.bb.abb.R209 - footprint=0402 - npins=2 - R211: # part of the voodoo "internal" VCXO circuit hier=mob.core.rf.Rita_vcxo.vcxo_passive.R211
--- a/venus/src/core/abb_block.v Mon Nov 22 09:54:48 2021 +0000 +++ b/venus/src/core/abb_block.v Mon Nov 22 19:19:59 2021 +0000 @@ -74,7 +74,7 @@ input VBATS, VCCS, VCHG; /* nets inside this module */ -wire UPR, VLMEM, Vabb; +wire UPR, Vabb; wire IBIAS, VREF; wire BULIM, BULIP, BULQM, BULQP; wire VBACKUP; @@ -168,7 +168,7 @@ .VDR(VDR), .VDX(VDX), .VFS(VFS), - .VLMEM(VLMEM), + .VLMEM(UPR), .VLRTC(GND), .VRABB(Vabb), .VRDBB(Vdbb), @@ -201,13 +201,7 @@ /* UPR bypass cap */ capacitor C208 (UPR, GND); -/* - * VLMEM is pulled up to UPR, and we are eliminating the pull-down option - * on FC Venus - our LCD wiring is incompatible with 1.8V MEMIF. - */ -resistor R209 (VLMEM, UPR); - -/* nTESTRESET also needs to be pulled up to UPR */ +/* nTESTRESET needs to be pulled up to UPR */ resistor R208 (nTESTRESET, UPR); /* IBIAS and VREF */