| Sat, 20 Nov 2021 04:32:50 +0000 |
Mychaela Falconia |
Venus src: jtag_if.v adapted from FCDEV3B
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| Fri, 19 Nov 2021 20:59:14 +0000 |
Mychaela Falconia |
Venus src: SIM socket block captured
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| Fri, 19 Nov 2021 20:35:10 +0000 |
Mychaela Falconia |
Venus src: add 74LVC1G04 inverting buffer for SIM_CD
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| Fri, 19 Nov 2021 20:10:46 +0000 |
Mychaela Falconia |
venus/src/periph/calypso_uart_in.v written
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| Fri, 19 Nov 2021 19:46:03 +0000 |
Mychaela Falconia |
Venus primitives: add logic IC subpackages
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| Fri, 19 Nov 2021 18:57:57 +0000 |
Mychaela Falconia |
Venus MCL: add 74LVC125A for Calypso UART inputs
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| Fri, 19 Nov 2021 06:48:25 +0000 |
Mychaela Falconia |
venus/src/periph/battery.v: adapted from FCDEV3B
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| Fri, 19 Nov 2021 06:44:53 +0000 |
Mychaela Falconia |
venus/src/periph/sma_wrap.v: unchanged from FCDEV3B
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| Fri, 19 Nov 2021 06:09:13 +0000 |
Mychaela Falconia |
Venus core: bring out SIM_CD
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| Fri, 19 Nov 2021 05:58:21 +0000 |
Mychaela Falconia |
Venus: first version of Verilog for the Calypso core
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| Fri, 19 Nov 2021 03:47:49 +0000 |
Mychaela Falconia |
Venus primitives: add TRRS jack
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| Fri, 19 Nov 2021 03:44:51 +0000 |
Mychaela Falconia |
Venus MCL: add audio jacks
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| Fri, 19 Nov 2021 03:07:48 +0000 |
Mychaela Falconia |
Venus primitives file started
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| Fri, 19 Nov 2021 01:43:41 +0000 |
Mychaela Falconia |
Venus MCL: add LEDs
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| Fri, 19 Nov 2021 01:02:52 +0000 |
Mychaela Falconia |
Venus MCL: connectors from FCDEV3B
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