FreeCalypso > hg > freecalypso-schem2

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Fri, 19 Nov 2021 20:10:46 +0000 Mychaela Falconia venus/src/periph/calypso_uart_in.v written
Fri, 19 Nov 2021 19:46:03 +0000 Mychaela Falconia Venus primitives: add logic IC subpackages
Fri, 19 Nov 2021 18:57:57 +0000 Mychaela Falconia Venus MCL: add 74LVC125A for Calypso UART inputs
Fri, 19 Nov 2021 06:48:25 +0000 Mychaela Falconia venus/src/periph/battery.v: adapted from FCDEV3B
Fri, 19 Nov 2021 06:44:53 +0000 Mychaela Falconia venus/src/periph/sma_wrap.v: unchanged from FCDEV3B
Fri, 19 Nov 2021 06:09:13 +0000 Mychaela Falconia Venus core: bring out SIM_CD
Fri, 19 Nov 2021 05:58:21 +0000 Mychaela Falconia Venus: first version of Verilog for the Calypso core
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