| Sat, 20 Nov 2021 19:44:59 +0000 |
Mychaela Falconia |
Venus src: USB domain captured
|
| Sat, 20 Nov 2021 17:48:18 +0000 |
Mychaela Falconia |
venus/src/usb: building blocks from DUART28
|
| Sat, 20 Nov 2021 09:10:02 +0000 |
Mychaela Falconia |
Venus primitives: additions for USB
|
| Sat, 20 Nov 2021 08:32:54 +0000 |
Mychaela Falconia |
Venus MCL: smaller package for USB EEPROM
|
| Sat, 20 Nov 2021 06:19:00 +0000 |
Mychaela Falconia |
Venus MCL: USB connector and ICs from DUART28
|
| Sat, 20 Nov 2021 05:45:37 +0000 |
Mychaela Falconia |
venus/src/top/mobile.v written
|
| Sat, 20 Nov 2021 04:32:50 +0000 |
Mychaela Falconia |
Venus src: jtag_if.v adapted from FCDEV3B
|
| Fri, 19 Nov 2021 20:59:14 +0000 |
Mychaela Falconia |
Venus src: SIM socket block captured
|
| Fri, 19 Nov 2021 20:35:10 +0000 |
Mychaela Falconia |
Venus src: add 74LVC1G04 inverting buffer for SIM_CD
|
| Fri, 19 Nov 2021 20:10:46 +0000 |
Mychaela Falconia |
venus/src/periph/calypso_uart_in.v written
|
| Fri, 19 Nov 2021 19:46:03 +0000 |
Mychaela Falconia |
Venus primitives: add logic IC subpackages
|
| Fri, 19 Nov 2021 18:57:57 +0000 |
Mychaela Falconia |
Venus MCL: add 74LVC125A for Calypso UART inputs
|
