| Sat, 27 Nov 2021 20:01:56 +0000 |
Mychaela Falconia |
add VBAT tap for calibration measurements
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| Sat, 27 Nov 2021 19:46:01 +0000 |
Mychaela Falconia |
LPG and PWL LEDs implemented
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| Sat, 27 Nov 2021 19:16:58 +0000 |
Mychaela Falconia |
MCL: prebiased transistor pair parts
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| Sat, 27 Nov 2021 18:34:05 +0000 |
Mychaela Falconia |
ON_nOFF indicator LED implemented
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| Sat, 27 Nov 2021 07:03:14 +0000 |
Mychaela Falconia |
keypad initial implementation
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| Sat, 27 Nov 2021 04:43:53 +0000 |
Mychaela Falconia |
Verilog src: preparations for adding the keypad
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| Sat, 27 Nov 2021 04:25:30 +0000 |
Mychaela Falconia |
MCL: preliminary part selection for keypad switches
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| Sat, 27 Nov 2021 02:46:19 +0000 |
Mychaela Falconia |
LCD subsystem integrated
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| Sat, 27 Nov 2021 02:09:46 +0000 |
Mychaela Falconia |
progress toward LCD integration
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| Sat, 27 Nov 2021 01:43:32 +0000 |
Mychaela Falconia |
MAX1916.v and lcd_module.v from lunalcd2
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| Sat, 27 Nov 2021 01:34:05 +0000 |
Mychaela Falconia |
74LVC2G125 buffer for BL control captured at MCL level
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| Sat, 27 Nov 2021 01:09:05 +0000 |
Mychaela Falconia |
MCL and primitives: LCD and MAX1916 from lunalcd2
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| Sat, 27 Nov 2021 00:25:20 +0000 |
Mychaela Falconia |
add top README
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| Fri, 26 Nov 2021 23:45:48 +0000 |
Mychaela Falconia |
add missing bypass caps for mobile domain peripherals
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| Fri, 26 Nov 2021 23:32:00 +0000 |
Mychaela Falconia |
charging_circuit structural module contains no connections to GND
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| Fri, 26 Nov 2021 23:18:12 +0000 |
Mychaela Falconia |
use buffer_slot_od primitive for slots of 74LVC2G07
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