log

age author description
Fri, 19 Nov 2021 20:59:14 +0000 Mychaela Falconia Venus src: SIM socket block captured
Fri, 19 Nov 2021 20:35:10 +0000 Mychaela Falconia Venus src: add 74LVC1G04 inverting buffer for SIM_CD
Fri, 19 Nov 2021 20:10:46 +0000 Mychaela Falconia venus/src/periph/calypso_uart_in.v written
Fri, 19 Nov 2021 19:46:03 +0000 Mychaela Falconia Venus primitives: add logic IC subpackages
Fri, 19 Nov 2021 18:57:57 +0000 Mychaela Falconia Venus MCL: add 74LVC125A for Calypso UART inputs
Fri, 19 Nov 2021 06:48:25 +0000 Mychaela Falconia venus/src/periph/battery.v: adapted from FCDEV3B
Fri, 19 Nov 2021 06:44:53 +0000 Mychaela Falconia venus/src/periph/sma_wrap.v: unchanged from FCDEV3B