log

age author description
Fri, 19 Nov 2021 06:09:13 +0000 Mychaela Falconia Venus core: bring out SIM_CD
Fri, 19 Nov 2021 05:58:21 +0000 Mychaela Falconia Venus: first version of Verilog for the Calypso core
Fri, 19 Nov 2021 03:47:49 +0000 Mychaela Falconia Venus primitives: add TRRS jack
Fri, 19 Nov 2021 03:44:51 +0000 Mychaela Falconia Venus MCL: add audio jacks
Fri, 19 Nov 2021 03:07:48 +0000 Mychaela Falconia Venus primitives file started
Fri, 19 Nov 2021 01:43:41 +0000 Mychaela Falconia Venus MCL: add LEDs