| Mon, 22 Nov 2021 09:54:48 +0000 |
Mychaela Falconia |
starpoints in core: commit to using pcb-rnd intnoconn
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| Mon, 22 Nov 2021 03:25:55 +0000 |
Mychaela Falconia |
charging LED circuit captured
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| Mon, 22 Nov 2021 03:03:15 +0000 |
Mychaela Falconia |
intnoconn approach to charging current sense resistor
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| Sun, 21 Nov 2021 20:20:38 +0000 |
Mychaela Falconia |
Venus src: charging circuit captured
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| Sun, 21 Nov 2021 08:58:43 +0000 |
Mychaela Falconia |
Venus MCL: use new ipc-diode.pinout, add SS34 for charging
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| Sun, 21 Nov 2021 08:40:13 +0000 |
Mychaela Falconia |
Venus MCL: add Q401 charging circuit MOSFET
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| Sun, 21 Nov 2021 03:14:56 +0000 |
Mychaela Falconia |
venus/src/Makefile: generate bound.unet
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| Sun, 21 Nov 2021 03:05:26 +0000 |
Mychaela Falconia |
Venus MCL: ready for first binding
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| Sun, 21 Nov 2021 02:14:49 +0000 |
Mychaela Falconia |
Venus MCL: first steps toward binding,
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| Sat, 20 Nov 2021 21:54:27 +0000 |
Mychaela Falconia |
Venus: reached the point of compiling sverp.unet
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| Sat, 20 Nov 2021 21:12:23 +0000 |
Mychaela Falconia |
Venus: preliminary choice of slide switch part for charging control
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| Sat, 20 Nov 2021 19:44:59 +0000 |
Mychaela Falconia |
Venus src: USB domain captured
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| Sat, 20 Nov 2021 17:48:18 +0000 |
Mychaela Falconia |
venus/src/usb: building blocks from DUART28
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| Sat, 20 Nov 2021 09:10:02 +0000 |
Mychaela Falconia |
Venus primitives: additions for USB
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| Sat, 20 Nov 2021 08:32:54 +0000 |
Mychaela Falconia |
Venus MCL: smaller package for USB EEPROM
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| Sat, 20 Nov 2021 06:19:00 +0000 |
Mychaela Falconia |
Venus MCL: USB connector and ICs from DUART28
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| Sat, 20 Nov 2021 05:45:37 +0000 |
Mychaela Falconia |
venus/src/top/mobile.v written
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| Sat, 20 Nov 2021 04:32:50 +0000 |
Mychaela Falconia |
Venus src: jtag_if.v adapted from FCDEV3B
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| Fri, 19 Nov 2021 20:59:14 +0000 |
Mychaela Falconia |
Venus src: SIM socket block captured
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| Fri, 19 Nov 2021 20:35:10 +0000 |
Mychaela Falconia |
Venus src: add 74LVC1G04 inverting buffer for SIM_CD
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| Fri, 19 Nov 2021 20:10:46 +0000 |
Mychaela Falconia |
venus/src/periph/calypso_uart_in.v written
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| Fri, 19 Nov 2021 19:46:03 +0000 |
Mychaela Falconia |
Venus primitives: add logic IC subpackages
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| Fri, 19 Nov 2021 18:57:57 +0000 |
Mychaela Falconia |
Venus MCL: add 74LVC125A for Calypso UART inputs
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| Fri, 19 Nov 2021 06:48:25 +0000 |
Mychaela Falconia |
venus/src/periph/battery.v: adapted from FCDEV3B
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| Fri, 19 Nov 2021 06:44:53 +0000 |
Mychaela Falconia |
venus/src/periph/sma_wrap.v: unchanged from FCDEV3B
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| Fri, 19 Nov 2021 06:09:13 +0000 |
Mychaela Falconia |
Venus core: bring out SIM_CD
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| Fri, 19 Nov 2021 05:58:21 +0000 |
Mychaela Falconia |
Venus: first version of Verilog for the Calypso core
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| Fri, 19 Nov 2021 03:47:49 +0000 |
Mychaela Falconia |
Venus primitives: add TRRS jack
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| Fri, 19 Nov 2021 03:44:51 +0000 |
Mychaela Falconia |
Venus MCL: add audio jacks
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| Fri, 19 Nov 2021 03:07:48 +0000 |
Mychaela Falconia |
Venus primitives file started
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