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annotate gsm-fw/nucleus/demo/irqshell.S @ 238:0b13839f782c

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tiffs IVA: lsino (non-specific) implemented
author Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
date Sun, 26 Jan 2014 23:32:42 +0000
parents afceeeb2cba1
children
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1 /*
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2 * FreeNucleus Calypso port by Michael Spacefalcon
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3 *
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4 * This assembly module contains IRQ handler shell
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5 * and some closely related support functions.
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6 *
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7 * The approach to IRQ handling implemented in the present version
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8 * is exactly the same as was found in XVilka's original nucleus_plus.tar.gz
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9 * code targeting OMAP1510. I personally consider it very dumb and
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10 * suboptimal, but the present version is merely a proof of concept -
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11 * changing as little as possible from our starting point will (hopefully)
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12 * make it easier to get this code to compile, link and maybe even run.
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13 */
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14
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15 #include "asm_defs.h"
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16 #include "calirq.h"
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17
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18 .code 32
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19
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20 /*
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21 **********************************
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22 * GLOBAL VARIABLE DECLARATIONS *
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23 **********************************
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24 */
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25
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26 .data
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27
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28 @ Define vector table used by INT_IRQ to branch to necessary ISR
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29
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30 .globl INT_IRQ_Vectors
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31 INT_IRQ_Vectors:
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32 .word INT_Interrupt_Shell @ Vector 0
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33 .word INT_Interrupt_Shell @ Vector 1
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34 .word INT_Timer_Interrupt @ Vector 2 - TIMER2
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35 .word INT_Interrupt_Shell @ Vector 3
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36 .word INT_Interrupt_Shell @ Vector 4
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37 .word INT_Interrupt_Shell @ Vector 5
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38 .word INT_Interrupt_Shell @ Vector 6
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39 .word INT_Interrupt_Shell @ Vector 7
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40 .word INT_Interrupt_Shell @ Vector 8
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41 .word INT_Interrupt_Shell @ Vector 9
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42 .word INT_Interrupt_Shell @ Vector 10
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43 .word INT_Interrupt_Shell @ Vector 11
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44 .word INT_Interrupt_Shell @ Vector 12
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45 .word INT_Interrupt_Shell @ Vector 13
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46 .word INT_Interrupt_Shell @ Vector 14
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47 .word INT_Interrupt_Shell @ Vector 15
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48 .word INT_Interrupt_Shell @ Vector 16
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49 .word INT_Interrupt_Shell @ Vector 17
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50 .word INT_Interrupt_Shell @ Vector 18
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51 .word INT_Interrupt_Shell @ Vector 19
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52 .word INT_Interrupt_Shell @ Vector 20
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53
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54 @ Define the order in which the interrupts will be executed by software(INT_IRQ)
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55 @ Level 1 Interrupt Handler
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56 .globl INT_IRQ_Priority
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57 INT_IRQ_Priority:
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58 .word 0
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59 .word 1
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60 .word 2
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61 .word 3
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62 .word 4
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63 .word 5
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64 .word 6
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65 .word 7
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66 .word 8
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67 .word 9
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68 .word 10
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69 .word 11
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70 .word 12
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71 .word 13
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72 .word 14
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73 .word 15
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74 .word 16
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75 .word 17
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76 .word 18
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77 .word 19
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78 .word 20
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79 INT_Priority_End:
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80
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81 .text
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82
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83 /*
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84 ************************************************************************
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85 *
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86 * FUNCTION
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87 *
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88 * INT_Setup_Vector
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89 *
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90 * DESCRIPTION
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91 *
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92 * This function sets up the specified vector with the new vector
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93 * value. The previous vector value is returned to the caller.
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94 *
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95 *
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96 * Major Revision:
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97 *
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98 * M. Kyle Craig, Accelerated Technology, Inc.
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99 *
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100 *
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101 *
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102 * CALLED BY
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103 *
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104 * Application
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105 * TCC_Register_LISR Register LISR for vector
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106 *
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107 * CALLS
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108 *
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109 * None
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110 *
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111 * INPUTS
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112 *
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113 * vector Vector number to setup
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114 * new Pointer to new assembly
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115 * language ISR
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116 *
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117 * OUTPUTS
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118 *
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119 * old vector contents
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120 *
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121 * HISTORY
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122 *
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123 * NAME DATE REMARKS
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124 *
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125 * W. Lamie 08-27-1994 Created initial version 1.0
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126 * D. Lamie 08-27-1994 Verified version 1.0
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127 *
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128 ************************************************************************
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129 */
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130
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131 @VOID *INT_Setup_Vector(INT vector, VOID *new)
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132 @{
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133
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134 .globl INT_Setup_Vector
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135 INT_Setup_Vector:
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136
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137 @VOID *old_vector; /* Old interrupt vector */
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138 @VOID **vector_table; /* Pointer to vector table */
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139
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140 @ Calculate the starting address of the actual vector table.
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141 @ vector_table = (VOID **) 0;
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142
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143 @ Pickup the old interrupt vector.
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144 @ old_vector = vector_table[vector];
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145 @
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146 @ Setup the new interrupt vector.
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147 @ vector_table[vector] = new;
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148 @
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149 @ Return the old interrupt vector.
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
150 @ return(old_vector);
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
151
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
152
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
153 LDR r2, =INT_IRQ_Vectors @ Load the vector table address
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
154 MOV r0, r0, LSL #2 @ Multiply vector by 4 to get offset into table
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
155 LDR r3, [r2,r0] @ Load the old pointer
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
156 STR r1, [r2,r0] @ Store the new pointer into the vector table
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
157
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
158 MOV r0, r3 @ Put the old pointer into the return register
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
159
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
160 BX lr @ Return to caller
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
161
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
162 @}
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
163
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
164 /*
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
165 ************************************************************************
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
166 *
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
167 * FUNCTION
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
168 *
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
169 * INT_Retrieve_Shell
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
170 *
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
171 * DESCRIPTION
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
172 *
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
173 * This function retrieves the pointer to the shell interrupt
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
174 * service routine. The shell interrupt service routine calls
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
175 * the LISR dispatch routine.
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
176 *
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
177 *
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
178 * Major Revision:
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
179 *
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
180 * M. Kyle Craig, Accelerated Technology, Inc.
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
181 *
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
182 *
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
183 *
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
184 * CALLED BY
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
185 *
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
186 * TCC_Register_LISR Register LISR for vector
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
187 *
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
188 * CALLS
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
189 *
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
190 * None
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
191 *
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
192 * INPUTS
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
193 *
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
194 * vector Vector number to setup
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
195 *
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
196 * OUTPUTS
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
197 *
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
198 * shell pointer
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
199 *
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
200 * HISTORY
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
201 *
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
202 * NAME DATE REMARKS
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
203 *
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
204 * W. Lamie 08-27-1994 Created initial version 1.0
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
205 * D. Lamie 08-27-1994 Verified version 1.0
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
206 *
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
207 ************************************************************************
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
208 */
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
209
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
210 @VOID *INT_Retrieve_Shell(INT vector)
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
211 @{
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
212
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
213 .globl INT_Retrieve_Shell
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
214 INT_Retrieve_Shell:
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
215
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
216 @ Return the LISR Shell interrupt routine.
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
217 @ return(INT_Vectors[vector]);
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
218
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
219 LDR r1, =INT_IRQ_Vectors @ Load the vector table address
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
220 MOV r0, r0, LSL #2 @ Multiply vector by 4 to get offset into table
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
221 LDR r0, [r1,r0] @ Load interrupt handler pointer into return register
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
222
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
223 BX lr @ Return to caller
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
224
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
225
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
226 @}
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
227
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
228 /*
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
229 ************************************************************************
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
230 *
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
231 * FUNCTION
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
232 *
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
233 * _INT_IRQ
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
234 *
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
235 * DESCRIPTION
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
236 *
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
237 * This routine is the board-specific section for
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
238 * level 1 interrupt handling
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
239 *
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
240 * CALLED BY
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
241 *
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
242 * None
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
243 *
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
244 * CALLS
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
245 *
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
246 * TMT_Timer_Interrupt
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
247 *
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
248 * INPUTS
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
249 *
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
250 * None
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
251 *
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
252 *
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
253 * OUTPUTS
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
254 *
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
255 * None
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
256 *
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
257 * HISTORY
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
258 *
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
259 * NAME DATE REMARKS
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
260 *
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
261 * B. Ronquillo 05-10-00 Created initial version 1.0
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
262 *
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
263 ************************************************************************
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
264 */
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
265
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
266 .globl _INT_IRQ
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
267 _INT_IRQ:
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
268
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
269 STMDB sp!,{r0-r4} @ Save r0-r4 on temporary IRQ stack
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
270 SUB lr,lr,#4 @ Adjust IRQ return address
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
271
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
272 /*
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
273 ********************************
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
274 * Begin Hardware Specific Code *
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
275 ********************************
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
276 */
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
277
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
278 LDR r3, =INTH_BASE_ADDR @ load Interrupt Control Base
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
279 @ Get enable register value
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
280 @ original instr was: LDR r4, [r3,#INT_CNTRL_MIR]
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
281 @ but on the Calypso we have to read two 16-bit regs
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
282 ldrh r0, [r3, #MASK_IT_REG1]
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
283 ldrh r1, [r3, #MASK_IT_REG2]
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
284 @ now combine them into a 32-bit word in r4 for the old code to work as-is
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
285 orr r4, r0, r1, lsl #16
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
286
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
287 /*
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
288 ******************************
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
289 * End Hardware Specific Code *
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
290 ******************************
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
291 */
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
292
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
293 STMDB sp!,{r4} @ Put the enable register value on the IRQ stack
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
294 MVN r4,#0 @ Start with 0xFFFFFFFF to allow nesting of interrupts
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
295
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
296 /*
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
297 ********************************
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
298 * Begin Hardware Specific Code *
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
299 ********************************
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
300 */
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
301
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
302 @ Read Pending reg
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
303 @ original instr was: LDR r2, [r3,#INT_CNTRL_ITR]
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
304 @ do the same trick as we did for the mask regs
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
305 ldrh r0, [r3, #IT_REG1]
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
306 ldrh r1, [r3, #IT_REG2]
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
307 orr r2, r0, r1, lsl #16
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
308
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
309 /*
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
310 ******************************
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
311 * End Hardware Specific Code *
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
312 ******************************
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
313 */
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
314
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
315 LDR r3, =INT_IRQ_Priority @ Get the Priority table address
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
316
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
317 IRQ_VECTOR_LOOP:
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
318 LDR r0, [r3,#0] @ Load first vector to be checked from priority table
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
319 MOV r1, #1 @ Build mask
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
320 MOV r1, r1, LSL r0 @ Use vector number to set mask to correct bit position
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
321 TST r1, r2 @ Test if pending bit is set
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
322 BNE IRQ_VECTOR_FOUND @ If bit is set, branch to found section...
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
323
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
324 BIC r4,r4,r1 @ Clear mask bit to keep higher priority ints active
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
325 ADD r3, r3, #4 @ Move to next word in the priority table
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
326 LDR r0, =INT_Priority_End @ Load the end address for the priority table
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
327 CMP r0, r3 @ Make sure not at the end of the table (shouldn't happen!)
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
328 BNE IRQ_VECTOR_LOOP @ Continue to loop if not at the end of the table
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
329
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
330 @ No bits in pending register set, restore registers and exit interrupt servicing
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
331 ADD sp,sp,#4 @ Adjust sp above IRQ enable value
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
332 LDMIA sp!,{r0-r4} @ Restore r0-r4
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
333 STMDB sp!,{lr} @ Put return address for IRQ on stack
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
334 LDMIA sp!,{pc}^ @ return to the point of the exception and restore SPSR
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
335
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
336 IRQ_VECTOR_FOUND:
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
337
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
338 /*
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
339 ********************************
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
340 * Begin Hardware Specific Code *
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
341 ********************************
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
342 */
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
343
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
344 LDR r3, =INTH_BASE_ADDR @ load Interrupt Control Base
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
345
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
346 MVN r2, r1 @ Get the inverse of the interrupt vector
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
347 @ Write a zero to the interrupt being handled (IT_REGn)
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
348 cmp r0, #16
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
349 strloh r2, [r3, #IT_REG1]
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
350 mov r2, r2, lsr #16
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
351 strhsh r2, [r3, #IT_REG2]
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
352
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
353 @ Read the Mask reg - just like we did before
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
354 ldrh r1, [r3, #MASK_IT_REG1]
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
355 ldrh r2, [r3, #MASK_IT_REG2]
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
356 orr r2, r1, r2, lsl #16
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
357 @ was LDR r2, [r3,#INT_CNTRL_MIR]
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
358
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
359 ORR r4, r2, r4 @ Turn off lower priority pending bits and currently masked bits
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
360
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
361 @ write both mask registers
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
362 @ was STR r4, [r3,#INT_CNTRL_MIR]
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
363 strh r4, [r3, #MASK_IT_REG1]
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
364 mov r1, r4, lsr #16
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
365 strh r1, [r3, #MASK_IT_REG2]
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
366
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
367 MOV r1, #1 @ Clear the pending interrupt
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
368 STRH r1, [r3,#IRQ_CTRL] @ by writing a 1 to the Control Reg
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
369
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
370 /*
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
371 ******************************
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
372 * End Hardware Specific Code *
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
373 ******************************
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
374 */
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
375
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
376 LDR r3, =INT_IRQ_Vectors @ Get IRQ vector table address
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
377 MOV r2, r0, LSL #2 @ Multiply vector by 4 to get offset into table
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
378 ADD r3, r3, r2 @ Adjust vector table address to correct offset
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
379 LDR r2, [r3,#0] @ Load branch address from vector table
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
380
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
381 MOV PC, r2 @ Jump to correct branch location based on vector table
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
382
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
383 @ END: INT_IRQ
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
384
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
385 /*
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
386 ************************************************************************
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
387 *
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
388 * FUNCTION
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
389 *
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
390 * INT_Interrupt_Shell
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
391 *
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
392 * DESCRIPTION
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
393 *
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
394 * Handles all interrupts which use NU_Register_LISR.
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
395 *
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
396 *
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
397 * CALLED BY
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
398 *
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
399 * INT_IRQ
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
400 *
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
401 * CALLS
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
402 *
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
403 * TCT_Dispatch_LISR
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
404 * TCT_Interrupt_Context_Restore
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
405 *
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
406 * INPUTS
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
407 *
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
408 * vector (register r0)
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
409 *
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
410 * OUTPUTS
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
411 *
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
412 * None
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
413 ************************************************************************
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
414 */
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
415
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
416 .globl INT_Interrupt_Shell
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
417 INT_Interrupt_Shell:
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
418
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
419 MOV r4,lr @ Put IRQ return address into r4
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
420
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
421 BL TCT_Interrupt_Context_Save
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
422
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
423 BL TCC_Dispatch_LISR
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
424
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
425 MRS r1,CPSR @ Pickup current CPSR
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
426 BIC r1,r1,#MODE_MASK @ Clear the mode bits
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
427 ORR r1,r1,#(IRQ_MODE_OR_LOCKOUT) @ Set the IRQ mode bits and Lockout interrupts
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
428 MSR CPSR,r1 @ Lockout interrupts/change to IRQ mode
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
429
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
430 /*
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
431 ********************************
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
432 * Begin Hardware Specific Code *
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
433 ********************************
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
434 */
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
435 LDMIA sp!,{r1} @ Get IRQ enable value off IRQ stack
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
436
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
437 LDR r2, =INTH_BASE_ADDR @ Get IRQ0 base register address
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
438 @ write it into both mask regs
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
439 @was STR r1,[r2,#INT_CNTRL_MIR]
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
440 strh r1, [r2, #MASK_IT_REG1]
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
441 mov r1, r1, lsr #16
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
442 strh r1, [r2, #MASK_IT_REG2]
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
443 /*
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
444 ******************************
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
445 * End Hardware Specific Code *
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
446 ******************************
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
447 */
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
448
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
449 MRS r1,CPSR @ Pickup current CPSR
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
450 BIC r1,r1,#MODE_MASK @ Clear the mode bits
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
451 ORR r1,r1,#SUP_MODE @ Set the SVC mode bits
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
452 MSR CPSR,r1 @ Change to SVC mode
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
453
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
454 B TCT_Interrupt_Context_Restore
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
455
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
456 /*
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
457 ************************************************************************
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
458 *
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
459 * FUNCTION
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
460 *
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
461 * INT_Timer_Interrupt
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
462 *
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
463 * DESCRIPTION
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
464 *
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
465 * This routine is the board-specific section of the timer
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
466 * interrupt handling
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
467 *
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
468 * CALLED BY
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
469 *
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
470 * None
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
471 *
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
472 * CALLS
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
473 *
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
474 * TMT_Timer_Interrupt
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
475 *
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
476 * INPUTS
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
477 *
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
478 * None
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
479 *
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
480 *
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
481 * OUTPUTS
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
482 *
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
483 * None
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
484 *
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
485 * HISTORY
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
486 *
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
487 * NAME DATE REMARKS
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
488 *
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
489 * B.Ronquillo 05-10-00 Created initial version 1.0
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
490 *
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
491 ************************************************************************
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
492 */
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
493
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
494 .globl INT_Timer_Interrupt
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
495 INT_Timer_Interrupt:
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
496
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
497 /*
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
498 ********************************
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
499 * Begin Hardware Specific Code *
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
500 ********************************
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
501 * Clear the pending timer interrupt
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
502 *
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
503 * This is done in the INT_IRQ function by writing a zero to the
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
504 * timer bit.
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
505 *
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
506 ******************************
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
507 * End Hardware Specific Code *
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
508 ******************************
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
509 */
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
510
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
511 MOV r4,lr @ Put IRQ return address into r4
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
512
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
513 BL TCT_Interrupt_Context_Save
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
514
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
515 BL TMT_Timer_Interrupt @ Call the timer interrupt
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
516 @ processing.
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
517
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
518 MRS r1,CPSR @ Pickup current CPSR
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
519 BIC r1,r1,#MODE_MASK @ Clear the mode bits
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
520 ORR r1,r1,#IRQ_MODE @ Set the IRQ mode bits
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
521 MSR CPSR,r1 @ Change to IRQ mode
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
522
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
523 /*
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
524 ********************************
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
525 * Begin Hardware Specific Code *
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
526 ********************************
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
527 */
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
528 LDMIA sp!,{r1} @ Get IRQ enable value off IRQ stack
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
529
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
530 LDR r2, =INTH_BASE_ADDR @ Get IRQ0 base register address
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
531 @ write it into both mask regs
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
532 @was STR r1,[r2,#INT_CNTRL_MIR]
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
533 strh r1, [r2, #MASK_IT_REG1]
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
534 mov r1, r1, lsr #16
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
535 strh r1, [r2, #MASK_IT_REG2]
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
536 /*
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
537 ******************************
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
538 * End Hardware Specific Code *
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
539 ******************************
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
540 */
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
541
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
542 MRS r1,CPSR @ Pickup current CPSR
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
543 BIC r1,r1,#MODE_MASK @ Clear the mode bits
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
544 ORR r1,r1,#SUP_MODE @ Set the SVC mode bits
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
545 MSR CPSR,r1 @ Change to SVC mode
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
546
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
547 B TCT_Interrupt_Context_Restore
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
548
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
549 @}
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
550 @ End of INT_Timer_Interrupt
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
551
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
552 /*
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
553 * INT_Interrupt_Init function written by Michael Spacefalcon
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
554 * for the FreeNucleus Calypso port - takes the place of
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
555 * INT_Install_Vector_Table, called from INT_Initialize.
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
556 */
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
557
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
558 .globl INT_Interrupt_Init
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
559 INT_Interrupt_Init:
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
560
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
561 @ first mask all interrupts in the INTH
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
562
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
563 ldr r0, =INTH_BASE_ADDR
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
564 mvn r1, #0
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
565 strh r1, [r0, #MASK_IT_REG1]
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
566 strh r1, [r0, #MASK_IT_REG2]
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
567
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
568 @ now install our IRQ vector into the magic IRAM jump table slot
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
569
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
570 ldr r0, =_INT_IRQ
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
571 mov r1, #0x800000
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
572 str r0, [r1, #0x14]
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
573
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
574 @ we are done!
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
575 bx lr
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
576
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
577 /*
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
578 * Need to define an INT_Vectors_Loaded() function
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
579 * that returns 1.
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
580 */
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
581 .globl INT_Vectors_Loaded
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
582 INT_Vectors_Loaded:
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
583 mov r0, #1
947b1f473960 beginning of nuc-fw
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
584 bx lr