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annotate gsm-fw/L1/cfile/l1_small_asm.S @ 923:10b4bed10192

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gsm-fw/L1: fix for the DSP patch corruption bug The L1 code we got from the LoCosto fw contains a feature for DSP CPU load measurement. This feature is a LoCosto-ism, i.e., not applicable to earlier DBB chips (Calypso) with their respective earlier DSP ROMs. Most of the code dealing with that feature is conditionalized as #if (DSP >= 38), but one spot was missed, and the MCU code was writing into an API word dealing with this feature. In TCS211 this DSP API word happens to be used by the DSP code patch, hence that write was corrupting the patched DSP code.
author Mychaela Falconia <falcon@ivan.Harhan.ORG>
date Mon, 19 Oct 2015 17:13:56 +0000
parents 8d6062f4e7e4
children
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1 /*
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2 * Assembly code extracted out of TI's l1_small.c
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3 *
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4 * This code is correct ONLY for CHIPSET 10 or 11 as currently used
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5 * by FreeCalypso; see TI's original code for what changes would be
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6 * needed to support other CHIPSETs.
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7 */
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8
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9 .text
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10 .code 32
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11
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12 /*-------------------------------------------------------*/
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13 /* _GSM_Small_Sleep */
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14 /* (formerly INT_Small_Sleep) */
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15 /*-------------------------------------------------------*/
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16 /* */
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17 /* Description: small sleep */
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18 /* ------------ */
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19 /* Called by TCT_Schedule main loop of Nucleus */
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20 /*-------------------------------------------------------*/
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21
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22 #define SMALL_SLEEP 0x01
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23 #define ALL_SLEEP 0x04
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24 #define PWR_MNGT 0x01
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25
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26 .globl _GSM_Small_Sleep
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27 _GSM_Small_Sleep:
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28
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29 ldr r0,Switch
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30 ldr r0,[r0]
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31 ldrb r1,[r0]
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32 cmp r1,#PWR_MNGT
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33 bne TCT_Schedule_Loop
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34
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35 ldr r0,Mode
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36 ldr r0,[r0]
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37 ldrb r1,[r0]
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38 cmp r1,#SMALL_SLEEP
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39 beq Small_sleep_ok
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40 cmp r1,#ALL_SLEEP
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41 bne TCT_Schedule_Loop
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43 Small_sleep_ok:
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44
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45 // *****************************************************
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46 //reset the DEEP_SLEEP bit 12 of CNTL_ARM_CLK register
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47 // (Cf BUG_1278)
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48
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49 ldr r0,addrCLKM @ pick up CNTL_ARM_CLK register address
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50 ldrh r1,[r0] @ take the current value of the register
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51 orr r1,r1,#0x1000 @ reset the bit
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52 strh r1,[r0] @ store the result
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54 ldr r0,addrCLKM @ pick up CLKM clock register address
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55 ldrh r1,[r0] @ take the current value of the register
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56 bic r1,r1,#1 @ disable ARM clock
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57 strh r1,[r0]
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59 B TCT_Schedule_Loop @ Return to TCT_Schedule main loop
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61 addrCLKM: .word 0xfffffd00 @ CLKM clock register address
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62
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63 Mode: .word mode_authorized
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64 Switch: .word switch_PWR_MNGT