FreeCalypso > hg > freecalypso-sw

annotate rvinterf/include/etm.h @ 923:10b4bed10192

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gsm-fw/L1: fix for the DSP patch corruption bug The L1 code we got from the LoCosto fw contains a feature for DSP CPU load measurement. This feature is a LoCosto-ism, i.e., not applicable to earlier DBB chips (Calypso) with their respective earlier DSP ROMs. Most of the code dealing with that feature is conditionalized as #if (DSP >= 38), but one spot was missed, and the MCU code was writing into an API word dealing with this feature. In TCS211 this DSP API word happens to be used by the DSP code patch, hence that write was corrupting the patched DSP code.
author Mychaela Falconia <falcon@ivan.Harhan.ORG>
date Mon, 19 Oct 2015 17:13:56 +0000
parents 38c7078712ab
children
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1 /*
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2 * This header file contains various definitions for talking to ETM.
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3 */
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5 #define ETM_USE_ID 0x001E0004
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6
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7 /* ETM Module IDs */
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8 enum {
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9 ETM_TM3 = 0x00, // Use of old TM3 protocol
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10 ETM_CORE = 0x01,
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11 ETM_TMT = 0x02, // Pseudo module
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12 ETM_SH = 0x03, // Pseudo module
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13 ETM_TM3_MISC = 0x04, // Pseudo module - Target side
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14 ETM_RF = 0x05,
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15 ETM_IMEI = 0x06,
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16 ETM_FFS2 = 0x07,
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17 ETM_AUDIO = 0x08,
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18 ETM_TPU = 0x09, // Not official part ETM
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19 ETM_PWR = 0x0A,
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20 ETM_BT = 0x0B,
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21 ETM_L23 = 0x0C,
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22 ETM_RESERVED10 = 0x0D,
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23 ETM_RESERVED11 = 0x0E,
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24 ETM_RESERVED12 = 0x0F,
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26 ETM_CUST = 0xC0, // Customize id
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27 ETM_CUST1 = 0xC1, // Customize id
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28 ETM_CUST2 = 0xC2, // Customize id
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29 ETM_CUST3 = 0xC3, // Customize id
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30 ETM_CUST4 = 0xC4, // Customize id
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31 ETM_CUST5 = 0xC5, // Customize id
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32 ETM_CUST6 = 0xC6, // Customize id
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33 ETM_CUST7 = 0xC7, // Customize id
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34 ETM_CUST8 = 0xC8, // Customize id
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36 ETM_TEST = 0xAA, // used for test of dll's
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37 ETM_TASK = 0xEE, // ETM TASK in Target
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39 ETM_FFS1 = 0x70
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40 };
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41
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42 /* ETM_CORE opcodes */
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43 #define TMCORE_OPC_MEM 0x61
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44 #define TMCORE_OPC_ECHO 0x62
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45 #define TMCORE_OPC_RESET 0x63
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46 #define TMCORE_OPC_DEBUG 0x64
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47 #define TMCORE_OPC_VERSION 0x65
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48 #define TMCORE_OPC_CODEC_RD 0x66
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49 #define TMCORE_OPC_CODEC_WR 0x67
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50 #define TMCORE_OPC_DIEID 0x68
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52 #define MAX_MEMREAD_BYTES 238
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53 #define MAX_MEMREAD_16BIT 119