FreeCalypso > hg > freecalypso-sw
annotate gsm-fw/bsp/sim32.c @ 182:13a0348ffce4
rvinterf/etm: checkpointing not-yet-compilable code
author | Michael Spacefalcon <msokolov@ivan.Harhan.ORG> |
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date | Sun, 24 Nov 2013 06:59:09 +0000 |
parents | 5e0e41cd7c9f |
children | 1199cdf99c32 |
rev | line source |
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1 /* |
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2 * SIM32.C |
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3 * |
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4 * Pole Star SIM |
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5 * |
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6 * Target : ARM |
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7 * |
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8 * Copyright (c) Texas Instruments 1995 |
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9 * |
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10 */ |
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11 |
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12 #define SIM32_C 1 |
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13 |
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14 #include "chipset.cfg" |
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15 |
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16 #include "main/sys_types.h" |
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17 #include <assert.h> |
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18 #include "inth/iq.h" |
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19 #include "sim.h" |
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20 |
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21 |
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22 #ifdef SIM_DEBUG_TRACE |
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23 /* working buffer for NULL BYTE */ |
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24 extern SYS_UWORD8 SIM_dbg_null[]; |
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25 /* Nucleus variable given the current number of TDMA frames */ |
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26 extern SYS_UWORD32 IQ_FrameCount; |
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27 /* working variable to calculate the TDMA ecart */ |
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28 extern SYS_UWORD16 SIM_dbg_tdma_diff; |
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29 /* working variable storing the current number of TDMA frames elapsed */ |
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30 SYS_UWORD32 SIM_dbg_local_count; |
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31 #endif |
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32 |
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33 /* |
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34 * SIM_IntHandler |
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35 * |
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36 * Read cause of SIM interrupt : |
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37 * |
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38 * if receive buffer full, read char |
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39 * if transmitter empty, change direction, transmit a dummy char |
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40 * |
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41 */ |
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42 void SIM_IntHandler(void) |
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43 { |
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44 volatile unsigned short it, i, stat, conf1; |
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45 volatile SYS_UWORD8 ins; |
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46 volatile SYS_UWORD8 rx; |
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47 volatile SYS_UWORD8 nack; |
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48 volatile SYS_UWORD8 nack1; |
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49 |
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50 |
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51 SIM_PORT *p; |
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52 |
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53 p = &(Sim[0]); |
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54 |
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55 p->rxParityErr = 0; |
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56 it = p->c->it; |
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57 |
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58 if ((it & SIM_IT_ITRX) && !(p->c->maskit & SIM_MASK_RX)) // int on reception |
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59 { |
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60 stat = p->c->rx; |
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61 conf1 = p->conf1; |
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62 |
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63 #ifdef SIM_DEBUG_TRACE |
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64 if ((IQ_FrameCount - SIM_dbg_local_count) > SIM_dbg_tdma_diff) { |
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65 SIM_dbg_tdma_diff = IQ_FrameCount - SIM_dbg_local_count; |
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66 } |
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67 SIM_dbg_local_count = IQ_FrameCount; |
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68 #endif |
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69 |
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70 // Check if reception parity is enable |
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71 if (((conf1 & SIM_CONF1_CHKPAR) && ((stat & SIM_DRX_STATRXPAR) != 0))\ |
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72 || ((conf1 & SIM_CONF1_CHKPAR) == 0)) |
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73 { |
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74 rx = (SYS_UWORD8) (stat & 0x00FF); |
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75 ins = p->xbuf[1] & p->hw_mask; |
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76 nack = (~p->xbuf[1]) & p->hw_mask; |
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77 |
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78 switch (p->moderx) |
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79 { |
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80 case 0: //mode of normal reception without proc char (like PTS proc) |
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81 p->rbuf[p->rx_index++] = rx; |
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82 break; |
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83 |
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84 case 1: //mode wait for ACK |
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85 if ((rx & p->hw_mask) == ins) |
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86 { |
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87 p->moderx = 2; |
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88 } |
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89 else if ((rx & p->hw_mask) == nack) |
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90 { |
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91 p->moderx = 4; |
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92 } |
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93 else if (((rx & 0xF0) == 0x60) || ((rx & 0xF0) == 0x90)) |
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94 { |
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95 if (rx != 0x60) //in case of error code (SW1/SW2) returned by sim card |
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96 { |
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97 p->rSW12[p->SWcount++] = rx; |
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98 p->moderx = 5; |
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99 } |
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100 else |
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parents:
diff
changeset
|
101 { |
5e0e41cd7c9f
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parents:
diff
changeset
|
102 p->null_received = 1; |
5e0e41cd7c9f
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff
changeset
|
103 #ifdef SIM_DEBUG_TRACE |
5e0e41cd7c9f
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parents:
diff
changeset
|
104 SIM_dbg_null[0]++; |
5e0e41cd7c9f
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parents:
diff
changeset
|
105 #endif |
5e0e41cd7c9f
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parents:
diff
changeset
|
106 } |
5e0e41cd7c9f
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parents:
diff
changeset
|
107 } |
5e0e41cd7c9f
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parents:
diff
changeset
|
108 else |
5e0e41cd7c9f
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parents:
diff
changeset
|
109 { |
5e0e41cd7c9f
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parents:
diff
changeset
|
110 p->errorSIM = SIM_ERR_ABNORMAL_CASE2; |
5e0e41cd7c9f
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parents:
diff
changeset
|
111 } |
5e0e41cd7c9f
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parents:
diff
changeset
|
112 //if rx = 0x60 wait for ACK |
5e0e41cd7c9f
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parents:
diff
changeset
|
113 break; |
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parents:
diff
changeset
|
114 |
5e0e41cd7c9f
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parents:
diff
changeset
|
115 case 2: //mode reception by block |
5e0e41cd7c9f
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parents:
diff
changeset
|
116 p->rbuf[p->rx_index++] = rx; |
5e0e41cd7c9f
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parents:
diff
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|
117 |
5e0e41cd7c9f
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parents:
diff
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|
118 if(p->expected_data == 256) |
5e0e41cd7c9f
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parents:
diff
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|
119 { |
5e0e41cd7c9f
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parents:
diff
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|
120 if (p->rx_index == 0) |
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff
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|
121 { |
5e0e41cd7c9f
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parents:
diff
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|
122 p->moderx = 5; |
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parents:
diff
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|
123 } |
5e0e41cd7c9f
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parents:
diff
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|
124 } |
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parents:
diff
changeset
|
125 else |
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parents:
diff
changeset
|
126 { |
5e0e41cd7c9f
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parents:
diff
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|
127 if (p->rx_index == p->expected_data) |
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parents:
diff
changeset
|
128 { |
5e0e41cd7c9f
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parents:
diff
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|
129 p->moderx = 5; |
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parents:
diff
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|
130 } |
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parents:
diff
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|
131 } |
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parents:
diff
changeset
|
132 break; |
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parents:
diff
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|
133 |
5e0e41cd7c9f
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parents:
diff
changeset
|
134 case 3: //mode reception char by char. reception of proc char |
5e0e41cd7c9f
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff
changeset
|
135 if ((rx & p->hw_mask) == ins) |
5e0e41cd7c9f
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff
changeset
|
136 { |
5e0e41cd7c9f
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parents:
diff
changeset
|
137 p->moderx = 2; |
5e0e41cd7c9f
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff
changeset
|
138 } |
5e0e41cd7c9f
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parents:
diff
changeset
|
139 else if ((rx & p->hw_mask) == nack) |
5e0e41cd7c9f
gsm-fw/bsp/sim*.c: initial import from the Leonardo semi-src
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff
changeset
|
140 { |
5e0e41cd7c9f
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff
changeset
|
141 p->moderx = 4; |
5e0e41cd7c9f
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff
changeset
|
142 } //if rx = 0x60 wait for ACK |
5e0e41cd7c9f
gsm-fw/bsp/sim*.c: initial import from the Leonardo semi-src
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff
changeset
|
143 else if (rx == 0x60) |
5e0e41cd7c9f
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff
changeset
|
144 { |
5e0e41cd7c9f
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff
changeset
|
145 p->null_received == 1; |
5e0e41cd7c9f
gsm-fw/bsp/sim*.c: initial import from the Leonardo semi-src
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff
changeset
|
146 #ifdef SIM_DEBUG_TRACE |
5e0e41cd7c9f
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff
changeset
|
147 SIM_dbg_null[1]++; |
5e0e41cd7c9f
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff
changeset
|
148 #endif |
5e0e41cd7c9f
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parents:
diff
changeset
|
149 } |
5e0e41cd7c9f
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff
changeset
|
150 |
5e0e41cd7c9f
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff
changeset
|
151 break; |
5e0e41cd7c9f
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parents:
diff
changeset
|
152 |
5e0e41cd7c9f
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff
changeset
|
153 case 4: //mode reception char by char. reception of data |
5e0e41cd7c9f
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff
changeset
|
154 p->rbuf[p->rx_index++] = rx; |
5e0e41cd7c9f
gsm-fw/bsp/sim*.c: initial import from the Leonardo semi-src
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff
changeset
|
155 p->moderx = 3; //switch to receive proc char mode |
5e0e41cd7c9f
gsm-fw/bsp/sim*.c: initial import from the Leonardo semi-src
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff
changeset
|
156 |
5e0e41cd7c9f
gsm-fw/bsp/sim*.c: initial import from the Leonardo semi-src
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff
changeset
|
157 if(p->expected_data == 256) |
5e0e41cd7c9f
gsm-fw/bsp/sim*.c: initial import from the Leonardo semi-src
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff
changeset
|
158 { |
5e0e41cd7c9f
gsm-fw/bsp/sim*.c: initial import from the Leonardo semi-src
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff
changeset
|
159 if (p->rx_index == 0) |
5e0e41cd7c9f
gsm-fw/bsp/sim*.c: initial import from the Leonardo semi-src
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff
changeset
|
160 { |
5e0e41cd7c9f
gsm-fw/bsp/sim*.c: initial import from the Leonardo semi-src
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff
changeset
|
161 p->moderx = 5; |
5e0e41cd7c9f
gsm-fw/bsp/sim*.c: initial import from the Leonardo semi-src
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff
changeset
|
162 } |
5e0e41cd7c9f
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff
changeset
|
163 } |
5e0e41cd7c9f
gsm-fw/bsp/sim*.c: initial import from the Leonardo semi-src
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff
changeset
|
164 else |
5e0e41cd7c9f
gsm-fw/bsp/sim*.c: initial import from the Leonardo semi-src
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff
changeset
|
165 { |
5e0e41cd7c9f
gsm-fw/bsp/sim*.c: initial import from the Leonardo semi-src
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff
changeset
|
166 if (p->rx_index == p->expected_data) |
5e0e41cd7c9f
gsm-fw/bsp/sim*.c: initial import from the Leonardo semi-src
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff
changeset
|
167 { |
5e0e41cd7c9f
gsm-fw/bsp/sim*.c: initial import from the Leonardo semi-src
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff
changeset
|
168 p->moderx = 5; |
5e0e41cd7c9f
gsm-fw/bsp/sim*.c: initial import from the Leonardo semi-src
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff
changeset
|
169 } |
5e0e41cd7c9f
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff
changeset
|
170 } |
5e0e41cd7c9f
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff
changeset
|
171 break; |
5e0e41cd7c9f
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff
changeset
|
172 |
5e0e41cd7c9f
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff
changeset
|
173 case 5: //mode wait for procedure character except NULL |
5e0e41cd7c9f
gsm-fw/bsp/sim*.c: initial import from the Leonardo semi-src
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff
changeset
|
174 if ((rx != 0x60) || (p->SWcount != 0)) //treat NULL character only if arriving before SW1 SW2 |
5e0e41cd7c9f
gsm-fw/bsp/sim*.c: initial import from the Leonardo semi-src
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff
changeset
|
175 { |
5e0e41cd7c9f
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff
changeset
|
176 p->rSW12[p->SWcount++] = rx; |
5e0e41cd7c9f
gsm-fw/bsp/sim*.c: initial import from the Leonardo semi-src
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff
changeset
|
177 } |
5e0e41cd7c9f
gsm-fw/bsp/sim*.c: initial import from the Leonardo semi-src
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff
changeset
|
178 else |
5e0e41cd7c9f
gsm-fw/bsp/sim*.c: initial import from the Leonardo semi-src
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff
changeset
|
179 { |
5e0e41cd7c9f
gsm-fw/bsp/sim*.c: initial import from the Leonardo semi-src
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff
changeset
|
180 p->null_received = 1; |
5e0e41cd7c9f
gsm-fw/bsp/sim*.c: initial import from the Leonardo semi-src
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff
changeset
|
181 #ifdef SIM_DEBUG_TRACE |
5e0e41cd7c9f
gsm-fw/bsp/sim*.c: initial import from the Leonardo semi-src
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff
changeset
|
182 SIM_dbg_null[2]++; |
5e0e41cd7c9f
gsm-fw/bsp/sim*.c: initial import from the Leonardo semi-src
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff
changeset
|
183 #endif |
5e0e41cd7c9f
gsm-fw/bsp/sim*.c: initial import from the Leonardo semi-src
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff
changeset
|
184 } |
5e0e41cd7c9f
gsm-fw/bsp/sim*.c: initial import from the Leonardo semi-src
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff
changeset
|
185 |
5e0e41cd7c9f
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff
changeset
|
186 |
5e0e41cd7c9f
gsm-fw/bsp/sim*.c: initial import from the Leonardo semi-src
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff
changeset
|
187 break; |
5e0e41cd7c9f
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parents:
diff
changeset
|
188 |
5e0e41cd7c9f
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff
changeset
|
189 case 6: //give the acknowledge char |
5e0e41cd7c9f
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff
changeset
|
190 if (((rx & 0xF0) == 0x60) || ((rx & 0xF0) == 0x90)) |
5e0e41cd7c9f
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff
changeset
|
191 { |
5e0e41cd7c9f
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff
changeset
|
192 if (rx != 0x60) //in case of error code (SW1/SW2) returned by sim card |
5e0e41cd7c9f
gsm-fw/bsp/sim*.c: initial import from the Leonardo semi-src
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff
changeset
|
193 { |
5e0e41cd7c9f
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff
changeset
|
194 p->rSW12[p->SWcount++] = rx; |
5e0e41cd7c9f
gsm-fw/bsp/sim*.c: initial import from the Leonardo semi-src
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff
changeset
|
195 p->moderx = 5; |
5e0e41cd7c9f
gsm-fw/bsp/sim*.c: initial import from the Leonardo semi-src
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff
changeset
|
196 } |
5e0e41cd7c9f
gsm-fw/bsp/sim*.c: initial import from the Leonardo semi-src
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff
changeset
|
197 else |
5e0e41cd7c9f
gsm-fw/bsp/sim*.c: initial import from the Leonardo semi-src
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff
changeset
|
198 { |
5e0e41cd7c9f
gsm-fw/bsp/sim*.c: initial import from the Leonardo semi-src
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff
changeset
|
199 p->null_received = 1; |
5e0e41cd7c9f
gsm-fw/bsp/sim*.c: initial import from the Leonardo semi-src
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff
changeset
|
200 #ifdef SIM_DEBUG_TRACE |
5e0e41cd7c9f
gsm-fw/bsp/sim*.c: initial import from the Leonardo semi-src
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff
changeset
|
201 SIM_dbg_null[3]++; |
5e0e41cd7c9f
gsm-fw/bsp/sim*.c: initial import from the Leonardo semi-src
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff
changeset
|
202 #endif |
5e0e41cd7c9f
gsm-fw/bsp/sim*.c: initial import from the Leonardo semi-src
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff
changeset
|
203 } |
5e0e41cd7c9f
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff
changeset
|
204 } |
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205 else |
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206 { |
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207 p->ack = rx; |
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208 } |
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209 } |
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210 } |
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211 else |
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212 { |
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213 p->rxParityErr = 1; |
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214 } |
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215 } |
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216 |
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217 if ((it & SIM_IT_ITTX) && !(p->c->maskit & SIM_MASK_TX)) |
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218 { |
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219 #ifdef SIM_DEBUG_TRACE |
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220 SIM_dbg_local_count = IQ_FrameCount; |
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221 #endif |
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222 // check the transmit parity |
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223 stat = p->c->stat; |
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224 |
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225 |
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226 if ((stat & SIM_STAT_TXPAR) || ((p->conf1 & SIM_CONF1_CHKPAR) == 0)) //parity disable |
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227 { |
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228 if (p->xOut != (p->xIn - 1)) //if only one char transmitted (already transmitted) |
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229 { //just need to have confirmation of reception |
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230 if (p->xOut == (p->xIn - 2)) |
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231 { |
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232 p->xOut++; |
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233 p->c->tx = *(p->xOut); // transmit |
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234 |
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235 p->conf1 &= ~SIM_CONF1_TXRX; // return the direction |
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236 p->c->conf1 = p->conf1; |
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237 } |
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238 |
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239 if (p->xOut < (p->xIn - 2)) |
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240 { |
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241 p->xOut++; |
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242 p->c->tx = *(p->xOut); // transmit |
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243 } |
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244 } |
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245 } |
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246 else |
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247 { |
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248 p->c->tx = *(p->xOut); // transmit same char |
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249 p->txParityErr++; // count number of transmit parity errors |
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250 } |
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251 |
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252 } |
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253 |
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254 // Handle errors |
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255 if ((it & SIM_IT_ITOV) && !(p->c->maskit & SIM_MASK_OV)) |
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diff
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|
256 { |
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diff
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|
257 p->errorSIM = SIM_ERR_OVF; |
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|
258 |
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|
259 } |
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260 if ((it & SIM_IT_WT) && !(p->c->maskit & SIM_MASK_WT)) |
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|
261 { |
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diff
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|
262 p->errorSIM = SIM_ERR_READ; |
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|
263 } |
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|
264 |
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diff
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|
265 // Reset the card in case of NATR to let the program continue |
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|
266 if ((it & SIM_IT_NATR) && !(p->c->maskit & SIM_MASK_NATR)) |
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|
267 { |
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diff
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|
268 p->c->cmd = SIM_CMD_STOP; |
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|
269 p->errorSIM = SIM_ERR_NATR; |
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|
270 } |
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|
271 |
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|
272 #if ((CHIPSET == 2) || (CHIPSET == 3)) |
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|
273 // SIM card insertion / extraction |
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|
274 if ((it & SIM_IT_CD) && !(p->c->maskit & SIM_MASK_CD)) |
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|
275 { |
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|
276 stat = p->c->stat; |
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|
277 if ((stat & SIM_STAT_CD) != SIM_STAT_CD) |
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|
278 { |
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|
279 (p->RemoveFunc)(); |
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|
280 p->errorSIM = SIM_ERR_NOCARD; |
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|
281 } |
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|
282 } |
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|
283 #endif |
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|
284 } |
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|
285 |
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|
286 #if ((CHIPSET == 4) || (CHIPSET == 5) || (CHIPSET == 6) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 9) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12)) |
5e0e41cd7c9f
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|
287 /* |
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|
288 * SIM_CD_IntHandler |
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|
289 * |
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|
290 * Read cause of SIM interrupt : |
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|
291 * |
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|
292 */ |
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diff
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|
293 void SIM_CD_IntHandler(void) |
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|
294 { |
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|
295 volatile unsigned short it_cd, stat; |
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|
296 SIM_PORT *p; |
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|
297 |
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298 p = &(Sim[0]); |
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299 |
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300 p->rxParityErr = 0; |
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301 it_cd = p->c->it_cd; |
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|
302 |
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303 // SIM card insertion / extraction |
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|
304 if ((it_cd & SIM_IT_CD) && !(p->c->maskit & SIM_MASK_CD)) |
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305 { |
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306 stat = p->c->stat; |
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307 if ((stat & SIM_STAT_CD) != SIM_STAT_CD) |
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308 { |
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309 (p->RemoveFunc)(); |
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310 p->errorSIM = SIM_ERR_NOCARD; |
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311 } |
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312 } |
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313 } |
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314 #endif |
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315 |
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316 |
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317 // to force this module to be linked |
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318 SYS_UWORD16 SIM_Dummy(void) |
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319 { |
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320 |
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321 } |