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annotate gsm-fw/services/ffs/intelsbdrv.c @ 938:1db4da08b9b4

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gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
author Mychaela Falconia <falcon@ivan.Harhan.ORG>
date Sat, 31 Oct 2015 23:02:20 +0000
parents
children 62ca61292b77
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938
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
1 /******************************************************************************
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
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2 * Flash File System (ffs)
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
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3 * Idea, design and coding by Mads Meisner-Jensen, mmj@ti.com
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
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4 *
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
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5 * FFS AMD single bank low level flash driver RAM code
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
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6 *
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
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7 * $Id: intelsbdrv.c 1.13 Thu, 08 Jan 2004 15:05:23 +0100 tsj $
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
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8 *
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
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9 ******************************************************************************/
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
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10
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
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11 #include "ffs.cfg"
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
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12
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
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13 #include "ffs/ffs.h"
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
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14 #include "ffs/board/drv.h"
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
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15 #include "ffs/board/ffstrace.h"
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
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16
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
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17
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
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18 #define INTEL_UNLOCK_SLOW 1
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
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19
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
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20
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
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21 #undef tlw
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
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22 #define tlw(contents)
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
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23 #undef ttw
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
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24 #define ttw(contents)
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
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25
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
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26 // Status bits for Intel flash memory devices
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
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27 #define INTEL_STATE_MACHINE_DONE (1<<7)
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
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28 #define FLASH_READ(addr) (*(volatile uint16 *) (addr))
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
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29 #define FLASH_WRITE(addr, data) (*(volatile uint16 *) (addr)) = data
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
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30
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
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31 asm(" .label _ffsdrv_ram_intel_begin");
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
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32 asm(" .def _ffsdrv_ram_intel_begin");
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
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33
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
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34 uint32 intel_int_disable(void);
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
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35 void intel_int_enable(uint32 tmp);
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
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36
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
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37 /******************************************************************************
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
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38 * INTEL Single Bank Driver Functions
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
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39 ******************************************************************************/
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
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40 // Actually we should have disabled and enable the interrupts in this
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
41 // function, but when the interrupt functions are used Target don't run!
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
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42 // Anyway, currently the interrupts are already disabled at this point thus
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
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43 // it does not cause any problems.
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
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44 int ffsdrv_ram_intel_sb_init(void)
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
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45 {
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
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46 uint32 cpsr, i;
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
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47 volatile char *addr;
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
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48 uint16 status;
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
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49
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
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50 for (i = 0; i < dev.numblocks; i++)
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
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51 {
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
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52 addr = block2addr(i);
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
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53
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
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54 *addr = 0x50; // Intel Clear Status Register
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
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55 *addr = 0xFF; // Intel read array
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
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56
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
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57 *addr = 0x60; // Intel Config Setup
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
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58 *addr = 0xD0; // Intel Unlock Block
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
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59
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
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60 // Wait for unlock to finish
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
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61 do {
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
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62 status = FLASH_READ(addr);
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
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63 } while (!(status & INTEL_STATE_MACHINE_DONE));
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
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64
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
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65 *addr = 0x70; // Intel Read Status Register
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
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66 status = FLASH_READ(addr);
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
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67
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
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68 // Is there an erase suspended?
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
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69 if ((status & 0x40) != 0) {
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
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70 *addr = 0xD0; // Intel erase resume
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
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71
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
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72 *addr = 0x70; // Intel Read Status Register
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
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73 // wait for erase to finish
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
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74 do {
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
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75 status = FLASH_READ(addr);
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
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76 } while (!(status & INTEL_STATE_MACHINE_DONE));
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
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77 }
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
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78
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
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79 *addr = 0xFF; // Intel Read Array
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
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80 }
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
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81
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
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82 return 0;
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
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83 }
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
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84
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
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85 void ffsdrv_ram_intel_sb_write_halfword(volatile uint16 *addr, uint16 value)
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
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86 {
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
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87 uint32 cpsr;
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
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88
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
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89 ttw(ttr(TTrDrv, "wh(%x,%x)" NL, addr, value));
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
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90
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
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91 if (~*addr & value) {
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
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92 ttw(ttr(TTrFatal, "wh(%x,%x->%x) fatal" NL, addr, *addr, value));
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
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93 return;
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
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94 }
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
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95
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
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96 cpsr = intel_int_disable();
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
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97 tlw(led_on(LED_WRITE));
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
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98
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
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99 #if (INTEL_UNLOCK_SLOW == 1)
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
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100 *addr = 0x60; // Intel Config Setup
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
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101 *addr = 0xD0; // Intel Unlock Block
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
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102 #endif
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
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103
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
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104 *addr = 0x50; // Intel Clear Status Register
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
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105 *addr = 0x40; // Intel program byte/word
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
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106 *addr = value;
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
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107 while ((*addr & 0x80) == 0)
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
108 ;
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
109 *addr = 0xFF; // Intel read array
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
110 tlw(led_off(LED_WRITE));
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
111 intel_int_enable(cpsr);
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
112 }
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
113
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
114 void ffsdrv_ram_intel_sb_erase(uint8 block)
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
115 {
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
116 volatile char *addr;
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
117 uint32 cpsr;
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
118 uint16 poll;
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
119
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
120 ttw(ttr(TTrDrvEra, "e(%d)" NL, block));
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
121
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
122 addr = block2addr(block);
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
123
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
124 cpsr = intel_int_disable();
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
125 tlw(led_on(LED_ERASE));
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
126
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
127 #if (INTEL_UNLOCK_SLOW == 1)
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
128 *addr = 0x60; // Intel Config Setup
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
129 *addr = 0xD0; // Intel Unlock Block
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
130 #endif
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
131
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
132 *addr = 0x50; // Intel Clear Status Register
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
133 *addr = 0x20; // Intel Erase Setup
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
134 *addr = 0xD0; // Intel Erase Confirm
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
135 *addr = 0x70; // Intel Read Status Register
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
136
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
137 // Wait for erase to finish.
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
138 while ((*addr & 0x80) == 0) {
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
139 tlw(led_toggle(LED_ERASE));
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
140 // Poll interrupts, taking interrupt mask into account.
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
141 if (INT_REQUESTED)
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
142 {
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
143 // 1. suspend erase
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
144 // 2. enable interrupts
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
145 // .. now the interrupt code executes
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
146 // 3. disable interrupts
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
147 // 4. resume erase
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
148
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
149 tlw(led_on(LED_ERASE_SUSPEND));
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
150
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
151 *addr = 0xB0; // Intel Erase Suspend
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
152 *addr = 0x70; // Intel Read Status Register
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
153 while (((poll = *addr) & 0x80) == 0)
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
154 ;
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
155
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
156 // If erase is complete, exit immediately
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
157 if ((poll & 0x40) == 0)
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
158 break;
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
159
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
160 *addr = 0xFF; // Intel read array
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
161
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
162 tlw(led_off(LED_ERASE_SUSPEND));
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
163 intel_int_enable(cpsr);
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
164
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
165 // Other interrupts and tasks run now...
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
166
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
167 cpsr = intel_int_disable();
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
168 tlw(led_on(LED_ERASE_SUSPEND));
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
169
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
170 *addr = 0xD0; // Intel erase resume
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
171 // The following "extra" Read Status command is required because Intel has
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
172 // changed the specification of the W30 flash! (See "1.8 Volt Intel®
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
173 // Wireless Flash Memory with 3 Volt I/O 28F6408W30, 28F640W30, 28F320W30
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
174 // Specification Update")
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
175 *addr = 0x70; // Intel Read Status Register
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
176
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
177 tlw(led_off(LED_ERASE_SUSPEND));
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
178 }
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
179 }
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
180 *addr = 0xFF; // Intel read array
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
181
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
182 tlw(led_on(LED_ERASE));
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
183 tlw(led_off(LED_ERASE));
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
184 intel_int_enable(cpsr);
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
185 }
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
186
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
187 // TODO: remove below function, not in use anymore.
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
188 void ffsdrv_ram_intel_erase(uint8 block)
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
189 {
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
190 uint32 cpsr;
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
191 uint16 status;
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
192
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
193 ttw(ttr(TTrDrvErase, "e(%d)" NL, block));
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
194 tlw(led_on(LED_ERASE));
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
195
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
196 dev.addr = (uint16 *) block2addr(block);
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
197
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
198 cpsr = intel_int_disable();
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
199 dev.state = DEV_ERASE;
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
200
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
201 *dev.addr = 0x60; // Intel Config setup
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
202 *dev.addr = 0xD0; // Intel Unlock block
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
203
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
204 *dev.addr = 0x50; // Intel clear status register (not really necessary)
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
205 *dev.addr = 0x20; // Intel erase setup
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
206 *dev.addr = 0xD0; // Intel erase confirm
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
207
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
208 intel_int_enable(cpsr);
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
209
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
210 while ((*dev.addr & 0x80) == 0)
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
211 ;
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
212
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
213 *dev.addr = 0xFF; // Intel read array
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
214 dev.state = DEV_READ;
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
215 tlw(led_off(LED_WRITE));
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
216 }
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
217
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
218
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
219 /******************************************************************************
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
220 * Interrupt Enable/Disable
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
221 ******************************************************************************/
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
222
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
223 uint32 intel_int_disable(void)
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
224 {
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
225 asm(" .state16");
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
226 asm(" mov A1, #0xC0");
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
227 asm(" ldr A2, tct_intel_disable");
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
228 asm(" bx A2 ");
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
229
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
230 asm("tct_intel_disable .field _TCT_Control_Interrupts+0,32");
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
231 asm(" .global _TCT_Control_Interrupts");
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
232 }
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
233
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
234 void intel_int_enable(uint32 cpsr)
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
235 {
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
236 asm(" .state16");
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
237 asm(" ldr A2, tct_intel_enable");
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
238 asm(" bx A2 ");
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
239
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
240 asm("tct_intel_enable .field _TCT_Control_Interrupts+0,32");
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
241 asm(" .global _TCT_Control_Interrupts");
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
242 }
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
243
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
244 // Even though we have this end label, we cannot determine the number of
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
245 // constant/PC-relative data following the code!
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
246 asm(" .state32");
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
247 asm(" .label _ffsdrv_ram_intel_end");
1db4da08b9b4 gsm-fw/services/ffs/intelsbdrv.c: initial import from TCS211 source
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
diff changeset
248 asm(" .def _ffsdrv_ram_intel_end");