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annotate nuc-fw/bsp/init_target.c @ 115:1e41550feec5

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nuc-fw: Init_Target() reconstructed
author Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
date Sun, 27 Oct 2013 04:43:04 +0000
parents
children 8b0793c67f9f
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
rev   line source
115
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
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1 /*
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2 * Init_Target() is the first function called from Application_Initialize().
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3 * But unfortunately, our TCS211 semi-src has this function in a binary lib.
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4 * I was able to find a conditioned-out version in the LoCosto source that
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5 * seems to be a fit - so I'm going to massage it a bit to match the sequence
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6 * of operations seen in the disassembly of our reference binary.
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7 */
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8
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9 #include "../include/config.h"
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10 #include "../include/sys_types.h"
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11
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12 #include "mem.h"
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13 #include "clkm.h"
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14 #include "armio.h"
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15 #include "timer.h"
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16 #include "inth.h"
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17 #include "rhea_arm.h"
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18 #include "ulpd.h"
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19
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20 /* TPU_FREEZE is defined in l1_const.h */
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21 #include "../L1/include/l1_confg.h"
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22 #include "../L1/include/l1_const.h"
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23
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24 void Init_Target(void)
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25 {
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26 #if 1 //(PSP_STANDALONE == 0)
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27 // RIF/SPI rising edge clock for ULYSSE
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28 //--------------------------------------------------
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29 #if ((ANALOG == 1) || (ANALOG == 2) || (ANALOG == 3) || (ANALOG == 11))
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30 #if ((CHIPSET >= 3))
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31 #if (CHIPSET == 12)
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32 F_CONF_RIF_RX_RISING_EDGE;
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33 F_CONF_SPI_RX_RISING_EDGE;
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34 #elif (CHIPSET == 15)
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35 //do the DRP init here for Locosto
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36 #if (L1_DRP == 1)
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37 // drp_power_on(); This should be done after the script is downloaded.
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38 #endif
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39 #else
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40 #if (BOARD==35)
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41 *((volatile SYS_UWORD16 *) ASIC_CONF) = 0x2000;
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42 #else
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43 *((volatile SYS_UWORD16 *) ASIC_CONF) = 0x6000;
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44 #endif /* (BOARD == 35) */
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45 #endif
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46 #endif
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47 #endif /* ANLG(ANALOG)) */
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48
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49 #if 0 //(OP_L1_STANDALONE == 1)
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50 #if (BOARD == 40) || (BOARD == 41) || \
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51 (BOARD == 42) || (BOARD == 43) || (BOARD == 45)
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52 // enable 8 Ohm amplifier for audio on D-sample
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53 AI_ConfigBitAsOutput (1);
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54 AI_SetBit(1);
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55 #elif (BOARD == 70) || (BOARD == 71)
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56 //Locosto I-sample or UPP costo board.BOARD
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57 // Initialize the ARMIO bits as per the I-sample spec
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58 // FIXME
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59 #endif
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60 #endif /* (OP_L1_STANDALONE == 1) */
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61 #endif /* PSP_STANDALONE ==0 */
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62
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63 // Watchdog
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64 //--------------------------------------------------
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65 TM_DisableWatchdog(); /* Disable Watchdog */
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66 #if (CHIPSET == 12) || (CHIPSET == 15)
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67 TM_SEC_DisableWatchdog();
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68 #endif
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69
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70 #if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12) || (CHIPSET == 15))
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71
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72 /*
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73 * Enable/Disable of clock switch off for INTH, TIMER, BRIDGE and DPLL modules
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74 */
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75 // IRQ, Timer and bridge may SLEEP
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76 // In first step, same configuration as SAMSON
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77 //--------------------------------------------------
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78 #if (CHIPSET == 12)
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79 CLKM_INITCNTL(CLKM_IRQ_DIS | CLKM_TIMER_DIS | CLKM_BRIDGE_DIS | CLKM_DPLL_DIS);
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80 #elif (CHIPSET == 15)
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81 CLKM_INITCNTL(CLKM_IRQ_DIS | CLKM_TIMER_DIS | CLKM_CPORT_EN | CLKM_BRIDGE_DIS | 0x8000 ); /* CLKM_DPLL_DIS is remove by Ranga*/
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82
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83 #else
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84 CLKM_CNTL_OR(CLKM_IRQ_DIS | CLKM_TIMER_DIS);
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85
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86 // Select VTCXO input frequency
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87 //--------------------------------------------------
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88 CLKM_UNUSED_VTCXO_26MHZ;
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89
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90 // Rita RF uses 26MHz VCXO
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91 #if (RF_FAM == 12)
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92 CLKM_USE_VTCXO_26MHZ;
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93 #endif
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94 // Renesas RF uses 26MHz on F-sample but 13MHz on TEB
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95 #if (RF_FAM == 43) && (BOARD == 46)
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96 CLKM_USE_VTCXO_26MHZ;
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97 #endif
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98 #endif
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99
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100 // Control HOM/SAM automatic switching
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101 //--------------------------------------------------
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102 *((volatile unsigned short *) CLKM_CNTL_CLK) &= ~CLKM_EN_IDLE3_FLG;
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103
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104 /*
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105 * Disassembly of Init_Target() in init.obj in main.lib in the
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106 * Leonardo reference version reveals that the code does the
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107 * following at this point:
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108 */
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109 RHEA_INITRHEA(0,0,0xFF);
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110 DPLL_INIT_BYPASS_MODE(DPLL_BYPASS_DIV_1);
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111 DPLL_INIT_DPLL_CLOCK(DPLL_LOCK_DIV_1, 8);
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112 CLKM_InitARMClock(0x00, 2, 0); /* no low freq, no ext clock, div by 1 */
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113 /* at this point the original code sets up the memory wait states */
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114 /* we'll do it differently */
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115 RHEA_INITAPI(0,1);
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116 RHEA_INITARM(0,0);
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117 DPLL_SET_PLL_ENABLE;
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118
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119 /*
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120 * Disable and Clear all pending interrupts
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121 */
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122 #if (CHIPSET == 12) || (CHIPSET == 15)
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123 F_INTH_DISABLE_ALL_IT; // MASK all it
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124 F_INTH2_VALID_NEXT(C_INTH_IRQ); // reset current IT in INTH2 IRQ
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125 F_INTH_VALID_NEXT(C_INTH_IRQ); // reset current IT in INTH IRQ
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126 F_INTH_VALID_NEXT(C_INTH_FIQ); // reset current IT in INTH FIQ
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127 F_INTH_RESET_ALL_IT; // reset all IRQ/FIQ source
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128 #else
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129 INTH_DISABLEALLIT;
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130 INTH_RESETALLIT;
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
131 INTH_CLEAR; /* reset IRQ/FIQ source */
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
132 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
133
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
134 // INTH
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
135 //--------------------------------------------------
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
136 #if (CHIPSET == 12) || (CHIPSET == 15)
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
137 #if (GSM_IDLE_RAM != 0)
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
138 f_inth_setup((T_INTH_CONFIG *)a_inth_config_idle_ram); // setup configuration IT handlers
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
139 #else
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
140 f_inth_setup((T_INTH_CONFIG *)a_inth_config); // setup configuration IT handlers
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
141 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
142 #else
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
143 IQ_SetupInterrupts();
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
144 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
145
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
146 // DMA
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
147 //--------------------------------------------------
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
148 // channel0 = Arm, channel1 = Lead, channel2 = forced to Arm, channel3=forced to Arm, dma_burst = 0001, priority = same
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
149 #if 1 //(OP_L1_STANDALONE == 0)
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
150 DMA_ALLOCDMA(1,0,1,1); // Channel 1 used by DSP with RIF RX
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
151 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
152
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
153 /* CHIPSET = 4 or 7 or 8 or 10 or 11 or 12 */
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
154
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
155 #else
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
156
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
157 // RHEA Bridge
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
158 //--------------------------------------------------
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
159 // ACCES_FAC_0 = 0, ACCES_FAC_1 = 0 ,TIMEOUT = 0x7F
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
160 RHEA_INITRHEA(0,0,0x7F);
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
161
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
162 #if (CHIPSET == 6)
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
163 // WS_H = 1 , WS_L = 15
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
164 RHEA_INITAPI(1,15); // should be 0x01E1 for 65 Mhz
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
165 #else
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
166 // WS_H = 0 , WS_L = 7
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
167 RHEA_INITAPI(0,7); // should be 0x0101 for 65 Mhz
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
168 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
169
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
170 // Write_en_0 = 0 , Write_en_1 = 0
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
171 RHEA_INITARM(0,0);
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
172
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
173 // INTH
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
174 //--------------------------------------------------
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
175 INTH_DISABLEALLIT; // MASK all it
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
176 INTH_CLEAR; // reset IRQ/FIQ source
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
177 IQ_SetupInterrupts();
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
178
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
179 // DMA
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
180 //--------------------------------------------------
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
181 // channel0 = Arm, channel1 = Lead, dma_burst = 0001, priority = same
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
182 DMA_ALLOCDMA(1,0,1,1); // should be 0x25 (channel 1 = lead)
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
183
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
184 #if (CHIPSET == 6)
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
185 // Memory WS configuration for ULYSS/G1 (26 Mhz) board
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
186 //-----------------------------------------------------
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
187 MEM_INIT_CS2(2,MEM_DVS_16,MEM_WRITE_EN,0);
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
188 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
189
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
190 // CLKM
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
191 //--------------------------------------------------
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
192 CLKM_InitARMClock(0x00, 2); /* no low freq, no ext clock, div by 1 */
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
193
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
194 #if (CHIPSET == 6)
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
195 CLKM_INITCNTL(CLKM_IRQ_DIS | CLKM_BRIDGE_DIS | CLKM_TIMER_DIS | CLKM_VTCXO_26);
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
196 #else
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
197 CLKM_INITCNTL(CLKM_IRQ_DIS | CLKM_BRIDGE_DIS | CLKM_TIMER_DIS);
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
198 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
199
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
200 #endif /* CHIPSET = 4 or 7 or 8 or 10 or 11 or 12 */
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
201
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
202 // Freeze ULPD timer ....
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
203 //--------------------------------------------------
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
204 *((volatile SYS_UWORD16 *) ULDP_GSM_TIMER_INIT_REG ) = 0;
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
205 *((volatile SYS_UWORD16 *) ULDP_GSM_TIMER_CTRL_REG ) = TPU_FREEZE;
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
206
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
207 // reset INC_SIXTEEN and INC_FRAC
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
208 //--------------------------------------------------
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
209 #if 0 //(OP_L1_STANDALONE == 1)
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
210 l1ctl_pgm_clk32(DEFAULT_HFMHZ_VALUE,DEFAULT_32KHZ_VALUE);
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
211 #else
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
212 ULDP_INCSIXTEEN_UPDATE(132); //32768.29038 =>132, 32500 => 133
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
213 // 26000 --> 166
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
214 ULDP_INCFRAC_UPDATE(15840); //32768.29038 =>15840, 32500 => 21845
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
215 // 26000 --> 43691
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
216 #endif /* OP_L1_STANDALONE */
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
217
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
218 // program ULPD WAKE-UP ....
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
219 //=================================================
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
220 #if (CHIPSET == 2)
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
221 *((volatile SYS_UWORD16 *)ULDP_SETUP_FRAME_REG) = SETUP_FRAME; // 2 frame
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
222 *((volatile SYS_UWORD16 *)ULDP_SETUP_VTCXO_REG) = SETUP_VTCXO; // 31 periods
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
223 *((volatile SYS_UWORD16 *)ULDP_SETUP_SLICER_REG) = SETUP_SLICER; // 31 periods
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
224 *((volatile SYS_UWORD16 *)ULDP_SETUP_CLK13_REG) = SETUP_CLK13; // 31 periods
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
225 #else
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
226 *((volatile SYS_UWORD16 *)ULDP_SETUP_FRAME_REG) = SETUP_FRAME; // 3 frames
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
227 *((volatile SYS_UWORD16 *)ULDP_SETUP_VTCXO_REG) = SETUP_VTCXO; // 0 periods
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
228 *((volatile SYS_UWORD16 *)ULDP_SETUP_SLICER_REG) = SETUP_SLICER; // 31 periods
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
229 *((volatile SYS_UWORD16 *)ULDP_SETUP_CLK13_REG) = SETUP_CLK13; // 31 periods
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
230 *((volatile SYS_UWORD16 *)ULPD_SETUP_RF_REG) = SETUP_RF; // 31 periods
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
231 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
232
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
233 #if (CHIPSET == 15)
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
234 *((volatile SYS_UWORD16 *)ULPD_DCXO_SETUP_SLEEPN) = SETUP_SLEEPZ; // 0
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
235 *((volatile SYS_UWORD16 *)ULPD_DCXO_SETUP_SYSCLKEN) = SETUP_SYSCLKEN; // 255 clocks of 32 KHz for 7.8 ms DCXO delay for Locosto
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
236 *((volatile SYS_UWORD16 *)0xFFFEF192) = 0x1; //CLRZ
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
237 *((volatile SYS_UWORD16 *)0xFFFEF190) = 0x2; //SLPZ
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
238 *((volatile SYS_UWORD16 *)0xFFFEF18E)= 0x2; //SYSCLKEN
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
239 *((volatile SYS_UWORD16 *)0xFFFEF186) = 0x2; //CLK13_EN
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
240 *((volatile SYS_UWORD16 *)0xFFFEF18A) = 0x2; //DRP_DBB_SYSCLK
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
241 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
242
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
243 // Set Gauging versus HF (PLL)
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
244 //=================================================
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
245 ULDP_GAUGING_SET_HF; // Enable gauging versus HF
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
246 ULDP_GAUGING_HF_PLL; // Gauging versus PLL
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
247
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
248 // current supply for quartz oscillation
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
249 //=================================================
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
250 #if 0 //(OP_L1_STANDALONE == 1)
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
251 #if ((CHIPSET != 9) && (CHIPSET != 12) && (CHIPSET !=15)) // programming model changed for Ulysse C035, stay with default value
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
252 *(volatile SYS_UWORD16 *)QUARTZ_REG = 0x27;
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
253 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
254 #else
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
255 #if ((BOARD == 6) || (BOARD == 8) || (BOARD == 9) || (BOARD == 35) || (BOARD == 40) || (BOARD == 41))
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
256 *((volatile SYS_UWORD16 *)QUARTZ_REG) = 0x27;
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
257 #elif (BOARD == 7)
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
258 *((volatile SYS_UWORD16 *)QUARTZ_REG) = 0x24;
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
259 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
260 #endif /* OP_L1_STANDALONE */
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
261
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
262 // stop Gauging if any (debug purpose ...)
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
263 //--------------------------------------------------
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
264 if ( *((volatile SYS_UWORD16 *) ULDP_GAUGING_CTRL_REG) & ULDP_GAUGING_EN)
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
265 {
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
266 volatile int j;
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
267 ULDP_GAUGING_STOP; /* Stop the gauging */
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
268 /* wait for gauging it*/
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
269 // one 32khz period = 401 periods of 13Mhz
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
270 for (j=1; j<50; j++);
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
271 while (! (* (volatile SYS_UWORD16 *) ULDP_GAUGING_STATUS_REG) & ULDP_IT_GAUGING);
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
272 }
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
273
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
274 #if 1 //(OP_L1_STANDALONE == 0)
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
275 AI_ClockEnable ();
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
276
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
277 #if (BOARD == 7)
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
278 // IOs configuration of the B-Sample in order to optimize the power consumption
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
279 AI_InitIOConfig();
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
280
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
281 // Set LPG instead of DSR_MODEM
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
282 *((volatile SYS_UWORD16 *) ASIC_CONF) |= 0x40;
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
283 // Reset the PERM_ON bit of LCR_REG
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
284 *((volatile SYS_UWORD16 *) MEM_LPG) &= ~(0x80);
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
285 #elif ((BOARD == 8) || (BOARD == 9))
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
286 // IOs configuration of the C-Sample in order to optimize the power consumption
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
287 AI_InitIOConfig();
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
288
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
289 // set the debug latch to 0x00.
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
290 *((volatile SYS_UWORD8 *) 0x2800000) = 0x00;
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
291 #elif ((BOARD == 35) || (BOARD == 46))
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
292 AI_InitIOConfig();
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
293 // CSMI INTERFACE
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
294 // Initialize CSMI clients for GSM control
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
295 // and Fax/Data services
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
296 CSMI_Init();
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
297 GC_Initialize(); // GSM control initialization
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
298 CU_Initialize(); // Trace initialization
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
299 CF_Initialize(); // Fax/Data pre-initialization
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
300 #elif ((BOARD == 40) || (BOARD == 41))
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
301 // IOs configuration of the D-Sample in order to optimize the power consumption
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
302 AI_InitIOConfig();
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
303
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
304 #ifdef BTEMOBILE
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
305 // Reset BT chip by toggling the Island's nRESET_OUT signal
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
306 *((volatile SYS_UWORD16 *) 0xFFFFFD04) |= 0x04;
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
307 *((volatile SYS_UWORD16 *) 0xFFFFFD04) &= ~(0x4);
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
308 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
309
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
310 #if 0 // FreeCalypso
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
311 // set the debug latch to 0x0000.
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
312 *((volatile SYS_UWORD16 *) 0x2700000) = 0x0000;
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
313 #endif
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
314 #elif ((BOARD == 70) || (BOARD == 71))
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
315 AI_InitIOConfig();
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
316 /* Mark The System configuration According to I-Sample */
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
317 /* Adding GPIO Mux Setting Here */
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
318 pin_configuration_all(); // Init Tuned for Power Management
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
319 /* A22 is Enabled in int.s hence not Here */
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
320 /* FIXME: PULL_UP Enable and PULL UP Values Need to revisited */
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
321
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
322 /* Add code to find out the manufacture id of NOR flash*/
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
323
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
324 // Copy ffsdrv_device_id_read() function code to RAM. The only known
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
325 // way to determine the size of the code is to look either in the
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
326 // linker-generated map file or in the assember output file.
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
327 ffsdrv_copy_code_to_ram((UWORD16 *) detect_code,
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
328 (UWORD16 *) &ffsdrv_device_id_read,
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
329 sizeof(detect_code));
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
330
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
331 // Combine bit 0 of the thumb mode function pointer with the address
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
332 // of the code in RAM. Then call the detect function in RAM.
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
333 myfp = (pf_t) (((int) &ffsdrv_device_id_read & 1) | (int) detect_code);
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
334 (*myfp)(0x06000000, &manufact, device_id);
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
335
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
336 enable_ps_ram_burst();
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
337
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
338 if( 0x7e == device_id[0] )
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
339 {
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
340 enable_flash_burst();
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
341 flash_device_id = 0x7E;
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
342 }
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
343 else
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
344 {
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
345 enable_flash_burst_mirror();
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
346 flash_device_id = 0;
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
347 }
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
348
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
349 /* FreeCalypso: a bunch of dead code cut out */
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
350
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
351 #endif // BOARD
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
352
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
353 // Enable HW Timers 1 & 2
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
354 TM_EnableTimer (1);
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
355 TM_EnableTimer (2);
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
356
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
357 #endif /* (OP_L1_STANDALONE == 0) */
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
358
1e41550feec5 nuc-fw: Init_Target() reconstructed
Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
parents:
diff changeset
359 }