FreeCalypso > hg > freecalypso-sw
annotate gsm-fw/nucleus/demo/irqshell.S @ 530:25a7fe25864c
gsm-fw/L1/include: switch to LoCosto versions of all header files
author | Michael Spacefalcon <msokolov@ivan.Harhan.ORG> |
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date | Fri, 01 Aug 2014 16:38:35 +0000 |
parents | afceeeb2cba1 |
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rev | line source |
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1 /* |
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2 * FreeNucleus Calypso port by Michael Spacefalcon |
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3 * |
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4 * This assembly module contains IRQ handler shell |
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5 * and some closely related support functions. |
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6 * |
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7 * The approach to IRQ handling implemented in the present version |
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8 * is exactly the same as was found in XVilka's original nucleus_plus.tar.gz |
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9 * code targeting OMAP1510. I personally consider it very dumb and |
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10 * suboptimal, but the present version is merely a proof of concept - |
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11 * changing as little as possible from our starting point will (hopefully) |
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12 * make it easier to get this code to compile, link and maybe even run. |
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13 */ |
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14 |
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15 #include "asm_defs.h" |
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16 #include "calirq.h" |
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17 |
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18 .code 32 |
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19 |
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20 /* |
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21 ********************************** |
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22 * GLOBAL VARIABLE DECLARATIONS * |
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23 ********************************** |
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24 */ |
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25 |
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26 .data |
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27 |
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28 @ Define vector table used by INT_IRQ to branch to necessary ISR |
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29 |
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30 .globl INT_IRQ_Vectors |
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31 INT_IRQ_Vectors: |
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32 .word INT_Interrupt_Shell @ Vector 0 |
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33 .word INT_Interrupt_Shell @ Vector 1 |
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34 .word INT_Timer_Interrupt @ Vector 2 - TIMER2 |
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35 .word INT_Interrupt_Shell @ Vector 3 |
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36 .word INT_Interrupt_Shell @ Vector 4 |
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37 .word INT_Interrupt_Shell @ Vector 5 |
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38 .word INT_Interrupt_Shell @ Vector 6 |
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39 .word INT_Interrupt_Shell @ Vector 7 |
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40 .word INT_Interrupt_Shell @ Vector 8 |
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41 .word INT_Interrupt_Shell @ Vector 9 |
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42 .word INT_Interrupt_Shell @ Vector 10 |
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43 .word INT_Interrupt_Shell @ Vector 11 |
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44 .word INT_Interrupt_Shell @ Vector 12 |
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45 .word INT_Interrupt_Shell @ Vector 13 |
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46 .word INT_Interrupt_Shell @ Vector 14 |
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47 .word INT_Interrupt_Shell @ Vector 15 |
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48 .word INT_Interrupt_Shell @ Vector 16 |
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49 .word INT_Interrupt_Shell @ Vector 17 |
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50 .word INT_Interrupt_Shell @ Vector 18 |
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51 .word INT_Interrupt_Shell @ Vector 19 |
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52 .word INT_Interrupt_Shell @ Vector 20 |
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53 |
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54 @ Define the order in which the interrupts will be executed by software(INT_IRQ) |
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55 @ Level 1 Interrupt Handler |
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56 .globl INT_IRQ_Priority |
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57 INT_IRQ_Priority: |
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58 .word 0 |
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59 .word 1 |
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60 .word 2 |
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61 .word 3 |
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62 .word 4 |
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63 .word 5 |
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64 .word 6 |
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65 .word 7 |
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66 .word 8 |
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67 .word 9 |
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68 .word 10 |
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69 .word 11 |
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70 .word 12 |
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71 .word 13 |
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72 .word 14 |
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73 .word 15 |
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74 .word 16 |
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75 .word 17 |
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76 .word 18 |
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77 .word 19 |
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78 .word 20 |
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79 INT_Priority_End: |
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80 |
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81 .text |
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82 |
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83 /* |
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84 ************************************************************************ |
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85 * |
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86 * FUNCTION |
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87 * |
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88 * INT_Setup_Vector |
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89 * |
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90 * DESCRIPTION |
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91 * |
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92 * This function sets up the specified vector with the new vector |
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93 * value. The previous vector value is returned to the caller. |
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94 * |
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95 * |
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96 * Major Revision: |
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97 * |
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98 * M. Kyle Craig, Accelerated Technology, Inc. |
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99 * |
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100 * |
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101 * |
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102 * CALLED BY |
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103 * |
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104 * Application |
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105 * TCC_Register_LISR Register LISR for vector |
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106 * |
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107 * CALLS |
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108 * |
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109 * None |
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110 * |
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111 * INPUTS |
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112 * |
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113 * vector Vector number to setup |
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114 * new Pointer to new assembly |
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115 * language ISR |
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116 * |
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117 * OUTPUTS |
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118 * |
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119 * old vector contents |
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120 * |
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121 * HISTORY |
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122 * |
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123 * NAME DATE REMARKS |
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124 * |
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125 * W. Lamie 08-27-1994 Created initial version 1.0 |
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126 * D. Lamie 08-27-1994 Verified version 1.0 |
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127 * |
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128 ************************************************************************ |
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129 */ |
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130 |
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131 @VOID *INT_Setup_Vector(INT vector, VOID *new) |
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132 @{ |
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133 |
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134 .globl INT_Setup_Vector |
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135 INT_Setup_Vector: |
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136 |
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137 @VOID *old_vector; /* Old interrupt vector */ |
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138 @VOID **vector_table; /* Pointer to vector table */ |
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139 |
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140 @ Calculate the starting address of the actual vector table. |
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141 @ vector_table = (VOID **) 0; |
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142 |
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143 @ Pickup the old interrupt vector. |
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144 @ old_vector = vector_table[vector]; |
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145 @ |
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146 @ Setup the new interrupt vector. |
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147 @ vector_table[vector] = new; |
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148 @ |
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149 @ Return the old interrupt vector. |
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150 @ return(old_vector); |
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151 |
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152 |
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153 LDR r2, =INT_IRQ_Vectors @ Load the vector table address |
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154 MOV r0, r0, LSL #2 @ Multiply vector by 4 to get offset into table |
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155 LDR r3, [r2,r0] @ Load the old pointer |
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156 STR r1, [r2,r0] @ Store the new pointer into the vector table |
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157 |
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158 MOV r0, r3 @ Put the old pointer into the return register |
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159 |
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160 BX lr @ Return to caller |
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161 |
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162 @} |
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163 |
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164 /* |
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165 ************************************************************************ |
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166 * |
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167 * FUNCTION |
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168 * |
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169 * INT_Retrieve_Shell |
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170 * |
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171 * DESCRIPTION |
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172 * |
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173 * This function retrieves the pointer to the shell interrupt |
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174 * service routine. The shell interrupt service routine calls |
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175 * the LISR dispatch routine. |
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176 * |
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177 * |
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178 * Major Revision: |
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179 * |
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180 * M. Kyle Craig, Accelerated Technology, Inc. |
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181 * |
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182 * |
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183 * |
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184 * CALLED BY |
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185 * |
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186 * TCC_Register_LISR Register LISR for vector |
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187 * |
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188 * CALLS |
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189 * |
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190 * None |
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191 * |
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192 * INPUTS |
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193 * |
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194 * vector Vector number to setup |
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195 * |
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196 * OUTPUTS |
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197 * |
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198 * shell pointer |
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199 * |
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200 * HISTORY |
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201 * |
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202 * NAME DATE REMARKS |
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203 * |
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204 * W. Lamie 08-27-1994 Created initial version 1.0 |
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205 * D. Lamie 08-27-1994 Verified version 1.0 |
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206 * |
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207 ************************************************************************ |
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208 */ |
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209 |
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210 @VOID *INT_Retrieve_Shell(INT vector) |
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211 @{ |
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212 |
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213 .globl INT_Retrieve_Shell |
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214 INT_Retrieve_Shell: |
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215 |
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216 @ Return the LISR Shell interrupt routine. |
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217 @ return(INT_Vectors[vector]); |
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218 |
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219 LDR r1, =INT_IRQ_Vectors @ Load the vector table address |
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220 MOV r0, r0, LSL #2 @ Multiply vector by 4 to get offset into table |
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221 LDR r0, [r1,r0] @ Load interrupt handler pointer into return register |
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222 |
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223 BX lr @ Return to caller |
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224 |
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225 |
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226 @} |
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227 |
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228 /* |
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229 ************************************************************************ |
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230 * |
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231 * FUNCTION |
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232 * |
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233 * _INT_IRQ |
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234 * |
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235 * DESCRIPTION |
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236 * |
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237 * This routine is the board-specific section for |
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238 * level 1 interrupt handling |
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239 * |
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240 * CALLED BY |
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241 * |
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242 * None |
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243 * |
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244 * CALLS |
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245 * |
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246 * TMT_Timer_Interrupt |
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247 * |
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248 * INPUTS |
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249 * |
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250 * None |
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251 * |
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252 * |
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253 * OUTPUTS |
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254 * |
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255 * None |
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256 * |
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257 * HISTORY |
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258 * |
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259 * NAME DATE REMARKS |
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260 * |
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261 * B. Ronquillo 05-10-00 Created initial version 1.0 |
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262 * |
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263 ************************************************************************ |
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264 */ |
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265 |
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266 .globl _INT_IRQ |
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267 _INT_IRQ: |
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268 |
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269 STMDB sp!,{r0-r4} @ Save r0-r4 on temporary IRQ stack |
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270 SUB lr,lr,#4 @ Adjust IRQ return address |
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271 |
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272 /* |
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273 ******************************** |
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274 * Begin Hardware Specific Code * |
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275 ******************************** |
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276 */ |
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277 |
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278 LDR r3, =INTH_BASE_ADDR @ load Interrupt Control Base |
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279 @ Get enable register value |
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280 @ original instr was: LDR r4, [r3,#INT_CNTRL_MIR] |
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281 @ but on the Calypso we have to read two 16-bit regs |
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282 ldrh r0, [r3, #MASK_IT_REG1] |
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283 ldrh r1, [r3, #MASK_IT_REG2] |
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284 @ now combine them into a 32-bit word in r4 for the old code to work as-is |
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285 orr r4, r0, r1, lsl #16 |
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286 |
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287 /* |
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288 ****************************** |
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289 * End Hardware Specific Code * |
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290 ****************************** |
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291 */ |
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292 |
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293 STMDB sp!,{r4} @ Put the enable register value on the IRQ stack |
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294 MVN r4,#0 @ Start with 0xFFFFFFFF to allow nesting of interrupts |
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295 |
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296 /* |
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297 ******************************** |
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298 * Begin Hardware Specific Code * |
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299 ******************************** |
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300 */ |
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301 |
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302 @ Read Pending reg |
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303 @ original instr was: LDR r2, [r3,#INT_CNTRL_ITR] |
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304 @ do the same trick as we did for the mask regs |
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305 ldrh r0, [r3, #IT_REG1] |
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306 ldrh r1, [r3, #IT_REG2] |
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307 orr r2, r0, r1, lsl #16 |
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308 |
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309 /* |
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310 ****************************** |
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311 * End Hardware Specific Code * |
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312 ****************************** |
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313 */ |
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314 |
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315 LDR r3, =INT_IRQ_Priority @ Get the Priority table address |
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316 |
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317 IRQ_VECTOR_LOOP: |
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318 LDR r0, [r3,#0] @ Load first vector to be checked from priority table |
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319 MOV r1, #1 @ Build mask |
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320 MOV r1, r1, LSL r0 @ Use vector number to set mask to correct bit position |
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321 TST r1, r2 @ Test if pending bit is set |
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322 BNE IRQ_VECTOR_FOUND @ If bit is set, branch to found section... |
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323 |
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324 BIC r4,r4,r1 @ Clear mask bit to keep higher priority ints active |
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325 ADD r3, r3, #4 @ Move to next word in the priority table |
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326 LDR r0, =INT_Priority_End @ Load the end address for the priority table |
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327 CMP r0, r3 @ Make sure not at the end of the table (shouldn't happen!) |
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328 BNE IRQ_VECTOR_LOOP @ Continue to loop if not at the end of the table |
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329 |
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330 @ No bits in pending register set, restore registers and exit interrupt servicing |
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331 ADD sp,sp,#4 @ Adjust sp above IRQ enable value |
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332 LDMIA sp!,{r0-r4} @ Restore r0-r4 |
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333 STMDB sp!,{lr} @ Put return address for IRQ on stack |
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334 LDMIA sp!,{pc}^ @ return to the point of the exception and restore SPSR |
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335 |
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336 IRQ_VECTOR_FOUND: |
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337 |
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338 /* |
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339 ******************************** |
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340 * Begin Hardware Specific Code * |
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341 ******************************** |
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342 */ |
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343 |
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344 LDR r3, =INTH_BASE_ADDR @ load Interrupt Control Base |
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345 |
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346 MVN r2, r1 @ Get the inverse of the interrupt vector |
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347 @ Write a zero to the interrupt being handled (IT_REGn) |
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348 cmp r0, #16 |
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349 strloh r2, [r3, #IT_REG1] |
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350 mov r2, r2, lsr #16 |
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351 strhsh r2, [r3, #IT_REG2] |
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352 |
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353 @ Read the Mask reg - just like we did before |
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354 ldrh r1, [r3, #MASK_IT_REG1] |
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355 ldrh r2, [r3, #MASK_IT_REG2] |
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356 orr r2, r1, r2, lsl #16 |
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357 @ was LDR r2, [r3,#INT_CNTRL_MIR] |
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358 |
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359 ORR r4, r2, r4 @ Turn off lower priority pending bits and currently masked bits |
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360 |
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361 @ write both mask registers |
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362 @ was STR r4, [r3,#INT_CNTRL_MIR] |
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363 strh r4, [r3, #MASK_IT_REG1] |
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364 mov r1, r4, lsr #16 |
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365 strh r1, [r3, #MASK_IT_REG2] |
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366 |
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367 MOV r1, #1 @ Clear the pending interrupt |
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368 STRH r1, [r3,#IRQ_CTRL] @ by writing a 1 to the Control Reg |
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369 |
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370 /* |
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371 ****************************** |
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372 * End Hardware Specific Code * |
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373 ****************************** |
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374 */ |
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375 |
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376 LDR r3, =INT_IRQ_Vectors @ Get IRQ vector table address |
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377 MOV r2, r0, LSL #2 @ Multiply vector by 4 to get offset into table |
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378 ADD r3, r3, r2 @ Adjust vector table address to correct offset |
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379 LDR r2, [r3,#0] @ Load branch address from vector table |
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380 |
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381 MOV PC, r2 @ Jump to correct branch location based on vector table |
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382 |
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383 @ END: INT_IRQ |
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384 |
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385 /* |
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386 ************************************************************************ |
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387 * |
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388 * FUNCTION |
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389 * |
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390 * INT_Interrupt_Shell |
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391 * |
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392 * DESCRIPTION |
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393 * |
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394 * Handles all interrupts which use NU_Register_LISR. |
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395 * |
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396 * |
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397 * CALLED BY |
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398 * |
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399 * INT_IRQ |
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400 * |
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401 * CALLS |
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402 * |
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403 * TCT_Dispatch_LISR |
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404 * TCT_Interrupt_Context_Restore |
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405 * |
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406 * INPUTS |
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407 * |
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408 * vector (register r0) |
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409 * |
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410 * OUTPUTS |
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411 * |
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412 * None |
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413 ************************************************************************ |
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414 */ |
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415 |
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416 .globl INT_Interrupt_Shell |
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417 INT_Interrupt_Shell: |
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418 |
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419 MOV r4,lr @ Put IRQ return address into r4 |
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420 |
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421 BL TCT_Interrupt_Context_Save |
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422 |
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423 BL TCC_Dispatch_LISR |
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424 |
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425 MRS r1,CPSR @ Pickup current CPSR |
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426 BIC r1,r1,#MODE_MASK @ Clear the mode bits |
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427 ORR r1,r1,#(IRQ_MODE_OR_LOCKOUT) @ Set the IRQ mode bits and Lockout interrupts |
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428 MSR CPSR,r1 @ Lockout interrupts/change to IRQ mode |
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429 |
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430 /* |
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431 ******************************** |
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432 * Begin Hardware Specific Code * |
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433 ******************************** |
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434 */ |
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435 LDMIA sp!,{r1} @ Get IRQ enable value off IRQ stack |
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436 |
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437 LDR r2, =INTH_BASE_ADDR @ Get IRQ0 base register address |
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438 @ write it into both mask regs |
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439 @was STR r1,[r2,#INT_CNTRL_MIR] |
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440 strh r1, [r2, #MASK_IT_REG1] |
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441 mov r1, r1, lsr #16 |
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442 strh r1, [r2, #MASK_IT_REG2] |
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443 /* |
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444 ****************************** |
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445 * End Hardware Specific Code * |
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446 ****************************** |
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447 */ |
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448 |
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449 MRS r1,CPSR @ Pickup current CPSR |
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450 BIC r1,r1,#MODE_MASK @ Clear the mode bits |
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451 ORR r1,r1,#SUP_MODE @ Set the SVC mode bits |
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452 MSR CPSR,r1 @ Change to SVC mode |
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453 |
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454 B TCT_Interrupt_Context_Restore |
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455 |
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456 /* |
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457 ************************************************************************ |
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458 * |
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459 * FUNCTION |
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460 * |
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461 * INT_Timer_Interrupt |
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462 * |
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463 * DESCRIPTION |
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464 * |
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465 * This routine is the board-specific section of the timer |
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466 * interrupt handling |
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467 * |
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468 * CALLED BY |
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469 * |
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470 * None |
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471 * |
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472 * CALLS |
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473 * |
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474 * TMT_Timer_Interrupt |
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475 * |
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476 * INPUTS |
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477 * |
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478 * None |
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479 * |
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480 * |
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481 * OUTPUTS |
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482 * |
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483 * None |
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484 * |
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485 * HISTORY |
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486 * |
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487 * NAME DATE REMARKS |
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488 * |
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489 * B.Ronquillo 05-10-00 Created initial version 1.0 |
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490 * |
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491 ************************************************************************ |
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492 */ |
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|
493 |
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494 .globl INT_Timer_Interrupt |
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495 INT_Timer_Interrupt: |
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496 |
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497 /* |
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498 ******************************** |
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499 * Begin Hardware Specific Code * |
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500 ******************************** |
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501 * Clear the pending timer interrupt |
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502 * |
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503 * This is done in the INT_IRQ function by writing a zero to the |
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504 * timer bit. |
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505 * |
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506 ****************************** |
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507 * End Hardware Specific Code * |
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508 ****************************** |
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509 */ |
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510 |
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511 MOV r4,lr @ Put IRQ return address into r4 |
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|
512 |
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513 BL TCT_Interrupt_Context_Save |
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|
514 |
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515 BL TMT_Timer_Interrupt @ Call the timer interrupt |
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516 @ processing. |
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517 |
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518 MRS r1,CPSR @ Pickup current CPSR |
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519 BIC r1,r1,#MODE_MASK @ Clear the mode bits |
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520 ORR r1,r1,#IRQ_MODE @ Set the IRQ mode bits |
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521 MSR CPSR,r1 @ Change to IRQ mode |
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522 |
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523 /* |
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524 ******************************** |
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525 * Begin Hardware Specific Code * |
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526 ******************************** |
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527 */ |
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528 LDMIA sp!,{r1} @ Get IRQ enable value off IRQ stack |
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529 |
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530 LDR r2, =INTH_BASE_ADDR @ Get IRQ0 base register address |
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531 @ write it into both mask regs |
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532 @was STR r1,[r2,#INT_CNTRL_MIR] |
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533 strh r1, [r2, #MASK_IT_REG1] |
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534 mov r1, r1, lsr #16 |
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535 strh r1, [r2, #MASK_IT_REG2] |
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536 /* |
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537 ****************************** |
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538 * End Hardware Specific Code * |
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539 ****************************** |
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540 */ |
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541 |
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542 MRS r1,CPSR @ Pickup current CPSR |
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543 BIC r1,r1,#MODE_MASK @ Clear the mode bits |
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544 ORR r1,r1,#SUP_MODE @ Set the SVC mode bits |
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545 MSR CPSR,r1 @ Change to SVC mode |
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546 |
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547 B TCT_Interrupt_Context_Restore |
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548 |
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549 @} |
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550 @ End of INT_Timer_Interrupt |
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551 |
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552 /* |
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553 * INT_Interrupt_Init function written by Michael Spacefalcon |
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554 * for the FreeNucleus Calypso port - takes the place of |
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555 * INT_Install_Vector_Table, called from INT_Initialize. |
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556 */ |
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557 |
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558 .globl INT_Interrupt_Init |
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559 INT_Interrupt_Init: |
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560 |
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561 @ first mask all interrupts in the INTH |
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562 |
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563 ldr r0, =INTH_BASE_ADDR |
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564 mvn r1, #0 |
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565 strh r1, [r0, #MASK_IT_REG1] |
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566 strh r1, [r0, #MASK_IT_REG2] |
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567 |
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568 @ now install our IRQ vector into the magic IRAM jump table slot |
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569 |
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570 ldr r0, =_INT_IRQ |
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571 mov r1, #0x800000 |
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572 str r0, [r1, #0x14] |
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573 |
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574 @ we are done! |
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575 bx lr |
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576 |
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577 /* |
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578 * Need to define an INT_Vectors_Loaded() function |
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579 * that returns 1. |
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580 */ |
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581 .globl INT_Vectors_Loaded |
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582 INT_Vectors_Loaded: |
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583 mov r0, #1 |
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Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
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584 bx lr |